Patents by Inventor Luiz M. Franca-Neto

Luiz M. Franca-Neto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210124524
    Abstract: Embodiments of an improved memory architecture for processing data inside of a device are described. In some embodiments, the device can store neural network layers, such as a systolic flow engine, in non-volatile memory and/or a separate first memory. A processor of a host system can delegate the execution of a neural network to the device. Advantageously, neural network processing in the device can be scalable, with the ability to process large amounts of data.
    Type: Application
    Filed: January 6, 2021
    Publication date: April 29, 2021
    Inventors: Luiz M. Franca-Neto, Viacheslav Dubeyko
  • Patent number: 10929058
    Abstract: Embodiments of an improved memory architecture by processing data inside of the memory device are described. In some embodiments, the memory device can store neural network layers, such as a systolic flow engine, in non-volatile memory and/or a separate DRAM memory. Central processing unit (CPU) of a host system can delegate the execution of a neural network to the memory device. Advantageously, neural network processing in the memory device can be scalable, with the ability to process large amounts of data.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: February 23, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Luiz M. Franca-Neto, Viacheslav Dubeyko
  • Patent number: 10860477
    Abstract: A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 8, 2020
    Assignee: WESTERN DIGITAL TECNOLOGIES, INC.
    Inventors: Frank R. Chu, Luiz M. Franca-Neto, Timothy K. Tsai, Qingbo Wang
  • Patent number: 10796198
    Abstract: Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units (“DPUs”) that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: October 6, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20200311537
    Abstract: Embodiments of storage device architecture for processing data using machine learning are disclosed. In some embodiments, the storage device includes a separate I/O core and a neural network core. The storage device can create a copy of data streams in which the data is stored, and the neural network core can process the copy of the data streams in a neural network while the I/O core can perform read or write functions on the data streams.
    Type: Application
    Filed: March 25, 2019
    Publication date: October 1, 2020
    Inventors: Luiz M. Franca-Neto, Viacheslav Dubeyko
  • Publication number: 20200228411
    Abstract: Embodiments of the present disclosure generally relate to a cloud computing network and a method of transferring information among processing nodes in a cloud computing network. In one embodiment, a cloud computing network is disclosed herein. The cloud computing network includes a plurality of motherboards arranged in racks. Each individual motherboard includes a central hub and a plurality of processing nodes equipped to the central hub. Each processing node is configured to access memory or storage space of another processing node in the same motherboard by intermediation of the hub. The access is called a communication between a pair of processing nodes. The communication includes a string of information transmitted between processing nodes. The string of information has a plurality of frames. Each frame includes a plurality of time slots, wherein each time slot is allotted a specific node pair.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventor: Luiz M. FRANCA-NETO
  • Patent number: 10644958
    Abstract: Embodiments of the present disclosure generally relate to a cloud computing network and a method of transferring information among processing nodes in a cloud computing network. In one embodiment, a cloud computing network is disclosed herein. The cloud computing network includes a plurality of motherboards arranged in racks. Each individual motherboard includes a central hub and a plurality of processing nodes equipped to the central hub. Each processing node is configured to access memory or storage space of another processing node in the same motherboard by intermediation of the hub. The access is called a communication between a pair of processing nodes. The communication includes a string of information transmitted between processing nodes. The string of information has a plurality of frames. Each frame includes a plurality of time slots, wherein each time slot is allotted a specific node pair.
    Type: Grant
    Filed: January 30, 2016
    Date of Patent: May 5, 2020
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Luiz M. Franca-Neto
  • Patent number: 10514867
    Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data programmed into a plurality NVM cells is encoded prior to programming, and a range of programmability associated with each of the plurality of NVM cells is determined when the plurality of NVM cells are programmed A first error management scheme is then applied to NVM cells identified as limited-range programmable cells, and a second error management scheme is applied to NVM cells identified as full-range programmable cells, such that the second error management scheme is different than the first error management scheme.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: December 24, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventor: Luiz M. Franca-Neto
  • Patent number: 10460801
    Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: October 29, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Jeffrey Lille, Luiz M. Franca-Neto
  • Publication number: 20190244086
    Abstract: Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units (“DPUs”) that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.
    Type: Application
    Filed: December 27, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244105
    Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244082
    Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244085
    Abstract: Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units (“DPUs”) that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.
    Type: Application
    Filed: December 27, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244077
    Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244078
    Abstract: Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units (“DPUs”) that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.
    Type: Application
    Filed: December 27, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244106
    Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244058
    Abstract: Some embodiments include a special-purpose hardware accelerator that can perform specialized machine learning tasks during both training and inference stages. For example, this hardware accelerator uses a systolic array having a number of data processing units (“DPUs”) that are each connected to a small number of other DPUs in a local region. Data from the many nodes of a neural network is pulsed through these DPUs with associated tags that identify where such data was originated or processed, such that each DPU has knowledge of where incoming data originated and thus is able to compute the data as specified by the architecture of the neural network. These tags enable the systolic neural network engine to perform computations during backpropagation, such that the systolic neural network engine is able to support training.
    Type: Application
    Filed: December 27, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244081
    Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 8, 2019
    Inventor: Luiz M. Franca-Neto
  • Publication number: 20190244083
    Abstract: A method of computer processing is disclosed comprising receiving a data packet at a processing node of a neural network, performing a calculation of the data packet at the processing node to create a processed data packet, attaching a tag to the processed data packet, transmitting the processed data packet from the processing node to a receiving node during a systolic pulse, receiving the processed data packet at the receiving node, performing a clockwise convolution on the processed data packet and a counter clockwise convolution on the processed data packet, performing an adding function and backpropagating results of the performed sigmoid function to each of the processing nodes that originally processed the data packet.
    Type: Application
    Filed: May 16, 2018
    Publication date: August 8, 2019
    Inventors: Luiz M. Franca-Neto, Luis V. Cargnini
  • Patent number: 10361365
    Abstract: A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 23, 2019
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Luiz M. Franca-Neto, Ricardo Ruiz