Abstract: A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM, and error correction vector (ECV) information associated with the NVM is stored in an error tracking table (ETT) within one of a dynamic random access memory (DRAM) or a second NVM component. The ETT is then filtered with a Bloom filter to predict a subset of ETT entries that include a reporting of an error in the NVM. A parallel query of the NVM and the ETT is then performed, which includes a query of the NVM that yields a readout of the NVM, and a query of the ETT that is limited to a query of the subset of ETT entries predicted by the Bloom filter which yields a construction of an ECV corresponding to the readout of the NVM.

Abstract: An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data programmed into a plurality NVM cells is encoded prior to programming, and a range of programmability associated with each of the plurality of NVM cells is determined when the plurality of NVM cells are programmed A first error management scheme is then applied to NVM cells identified as limited-range programmable cells, and a second error management scheme is applied to NVM cells identified as full-range programmable cells, such that the second error management scheme is different than the first error management scheme.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.

Abstract: Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM, and error correction vector (ECV) information associated with the NVM is stored in an error tracking table (ETT) within one of a dynamic random access memory (DRAM) or a second NVM component. The ETT is then filtered with a Bloom filter to predict a subset of ETT entries that include a reporting of an error in the NVM. A parallel query of the NVM and the ETT is then performed, which includes a query of the NVM that yields a readout of the NVM, and a query of the ETT that is limited to a query of the subset of ETT entries predicted by the Bloom filter which yields a construction of an ECV corresponding to the readout of the NVM.

Abstract: A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.

Abstract: A method and a storage system are provided for implementing enhanced solid state storage class memory (eSCM) including a direct attached dual in line memory (DIMM) card containing Dynamic Random Access Memory (DRAM), and at least one 5 non-volatile memory, for example, Phase Change Memory (PCM), Resistive RAM (ReRAM), Spin-Transfer-Torque RAM (STT-RAM), and NAND Flash chips. An eSCM processor controls selectively allocating data among the DRAM, and the at least one non-volatile memory primarily based upon a data set size.

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Abstract: An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.

Abstract: An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

Abstract: The present disclosure generally relates to a high performance datacenter computer (HPDC) that utilized mmWave links to communicate between servers at opposing racks across the datacenter aisles. The HPDC includes stacks of servers with the stacks arranged in rows. The HPDC includes multiple rows. Within the stacks and rows, the various servers are wired together, but between opposing rows, mmWave technology is used to communicate.

Abstract: Embodiments of the present disclosure generally relate to a cloud computing network and a method of transferring information among processing nodes in a cloud computing network. In one embodiment, a cloud computing network is disclosed herein. The cloud computing network includes a plurality of motherboards arranged in racks. Each individual motherboard includes a central hub and a plurality of processing nodes equipped to the central hub. Each processing node is configured to access memory or storage space of another processing node in the same motherboard by intermediation of the hub. The access is called a communication between a pair of processing nodes. The communication includes a string of information transmitted between processing nodes. The string of information has a plurality of frames. Each frame includes a plurality of time slots, wherein each time slot is allotted a specific node pair.