Abstract: Embodiments of the present disclosure generally relate to a cloud computing network, or datacenter network, and a method of transferring information among processing nodes in a cloud computing network or datacenter. The network may include a hub that is coupled to a plurality of nodes so that data is transferred between nodes through the hub. Data from different nodes may be written into a slot within the hub, read, and then written into a slot within the destination node. Due to the proximity of the nodes to the hub, or even due to the amount of data to be written, the data may be written at different clock phases. The read may occur one or more clock cycles after the data has been written into the hub.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.

Abstract: A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.

Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.

Abstract: Embodiments of the present disclosure generally relate to electronic devices, and more specifically, to multi-level phase change devices. In one embodiment, a memory cell device is provided. The memory cell device generally includes a top surface, a bottom surface and a cell body between the top surface and the bottom surface. The cell body may include a plurality of phase change material layers, which may be used to store data of the cell. In another embodiment, a method of programming a memory cell is provided. The method generally may include applying a sequence of different pulses to each phase change material layer of the cell as the voltage of each pulse in the sequence is ratcheted down from the start of a write cycle to the end of a write cycle.

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.

Abstract: Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.

Abstract: A three-dimensional (3D) scalable magnetic memory array and a method for implementing the three-dimensional (3D) scalable magnetic memory array for use in Solid-State Drives (SSDs) are provided. A three-dimensional (3D) scalable magnetic memory array includes an interlayer dielectric (IDL) stack of word planes separated by a respective IDL. A plurality of pillar holes is formed in the IDL stack in a single etch step; each of the pillar holes including an oxide barrier coating, and a first conductor M1, and a second conductor M2 forming magnetic pillar memory cells. The first conductor M1 is formed of a magnetic material, and the second conductor M2 is more electrically conductive than the conductor M1; and each of the magnetic pillar memory cell inside the pillar holes have a programmable area using unpatterned programmable magnetic media proximate to a respective one of the word planes.

Abstract: A segregated media based magnetic memory pillar cell and a method for implementing the segregated media based magnetic memory pillar cell for use in Solid-State Drives (SSDs) are provided. The segregated media based magnetic memory pillar cell includes a first conductor M1 and a second conductor M2 with the second conductor M2 surrounded by the first conductor M1. The first conductor M1 is formed of a segregated magnetic media material defining multiple domains.

Abstract: An authorization and validation system and method for mobile financial transactions uses (1) historic Global Positioning System (GPS) and time at specific locations and (2) both visible and invisible prompts to allow access to assets and performance of financial transactions. Said system and method also determines when the mobile device, tablet or smart phone, is lost or is operated by an impersonator. Special attention is devoted when said system is engaged in determining whether the user is under threat or not.

Abstract: A magnetic memory array and a method for implementing the magnetic memory array for use in Solid-State Drives (SSDs) are provided. A plurality of magnetic pillar memory cells is formed using a deposition and/or growth process to produce a magnetic memory array substantially avoiding milling of magnetic materials.

Abstract: A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

Abstract: A semiconductor device includes at least a first semiconductor die and a second semiconductor die. The first semiconductor dies comprises a first and second side, and includes at least a first contact pad located on the first side of the first semiconductor die. The second semiconductor die comprises a first and second side, and includes at least a second contact pad located on the first side of the second semiconductor die, wherein the first semiconductor die is stacked on the second semiconductor die and wherein the first side of the first semiconductor die faces the first side of the second semiconductor die. At least one voltage-guided conductive filament is created between the first contact pad and the second contact pad.

Abstract: A system, apparatus and method for generating and honoring awards, points or credits where ownership of each properly created and labeled award, point or credit is manifested and confirmed by the ability of a client to change specific secret content in pre-determined field assigned to said award, point or credit. Said ability is granted upon demonstration of knowledge of the current content of said pre-determined field. A system capable of purchases of good or services using awards, point or credits. A system supporting transfers, deposits and remittances of awards, points or credits with anonymity and convenience similar to ordinary cash. A system whose enabling client computational resources can be downloaded as a software application and can be operated under yearly subscription fee.

Abstract: A method and apparatus are provided for implementing enhanced data read for multi-level cell (MLC) memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding. A data read back for data written to the MLC memory using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding is performed, higher voltage and lower voltage levels are compared, and respective data values are identified responsive to the compared higher voltage and lower voltage levels.