Patents by Inventor Luka Bodrozic

Luka Bodrozic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory controller with loopback test interface
    Patent number: 8301941
    Abstract: An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: October 30, 2012
    Assignee: Apple Inc.
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Memory Controller with Loopback Test Interface
    Publication number: 20120072787
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Application
    Filed: November 28, 2011
    Publication date: March 22, 2012
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Memory controller with loopback test interface
    Patent number: 8086915
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: December 27, 2011
    Assignee: Apple Inc.
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Memory Controller with Loopback Test Interface
    Publication number: 20110035560
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Application
    Filed: October 21, 2010
    Publication date: February 10, 2011
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Memory controller with loopback test interface
    Patent number: 7836372
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: November 16, 2010
    Assignee: Apple Inc.
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller
  • Memory Controller with Loopback Test Interface
    Publication number: 20080307276
    Abstract: In one embodiment, an apparatus comprises an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller is programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller is configured to receive a first write operation from the processor over the interconnect. The memory controller is configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller is further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Inventors: Luka Bodrozic, Sukalpa Biswas, Hao Chen, Sridhar P. Subramanian, James B. Keller