Patents by Inventor Lung-En Kuo

Lung-En Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120012904
    Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a silicon layer on the semiconductor substrate; performing a first photo-etching process on the silicon layer for forming a gate pattern; forming an epitaxial layer in the semiconductor substrate adjacent to two sides of the gate pattern; and performing a second photo-etching process on the gate pattern to form a slot in the gate pattern while using the gate pattern to physically separate the gate pattern into two gates.
    Type: Application
    Filed: July 15, 2010
    Publication date: January 19, 2012
    Inventors: Ming-Te Wei, Wen-Chen Wu, Lung-En Kuo, Po-Chao Tsao
  • Patent number: 7851370
    Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: December 14, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Min-Chieh Yang
  • Patent number: 7709275
    Abstract: A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: May 4, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Min-Chieh Yang, Lung-En Kuo
  • Publication number: 20090258500
    Abstract: A method of forming a pattern for a semiconductor device, in which, two hard masks are included between an upper spin-on glass (SOG) layer and a lower etching target layer. The SOG layer is etched twice through two different patterned photoresists respectively to form a fine pattern in the SOG layer. Subsequently, an upper hard mask is etched by utilizing the patterned SOG layer as an etching mask so the upper patterned hard mask can have a fine pattern with a sound shape and enough thickness. A lower hard mask and the etching target layer are thereafter etched by utilizing the upper patterned hard mask as an etching mask, so portions of the etching target layer that are covered by the two hard masks can be well protected from the etching processes.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 15, 2009
    Inventors: Min-Chieh Yang, Lung-En Kuo
  • Publication number: 20090081817
    Abstract: A patterning method is provided. In the patterning method, a film is formed on a substrate and a pre-layer information is measured. Next, an etching process is performed to etch the film. The etching process includes a main etching step, an etching endpoint detection step, an extension etching step and an over etching step. An extension etching time for performing the extension etching step is set within 10 seconds based on a predetermined correlation between an extension etching time and the pre-layer information, so as to achieve a required film profile.
    Type: Application
    Filed: September 25, 2007
    Publication date: March 26, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Jiunn-Hsiung Liao, Min-Chieh Yang