Patents by Inventor Lynne M. Gignac
Lynne M. Gignac has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090045484Abstract: An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kaushik Chanda, Lynne M. Gignac, Wai-Kin Li, Ping-Chuan Wang
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Patent number: 6979393Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ? or as high as 1/10. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.Type: GrantFiled: January 22, 2002Date of Patent: December 27, 2005Assignee: International Business Machines CorporationInventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
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Patent number: 6784485Abstract: A semiconductor device containing a diffusion barrier layer is provided. The semiconductor device includes at least a semiconductor substrate containing conductive metal elements; and, a diffusion barrier layer applied to at least a portion of the substrate in contact with the conductive metal elements, the diffusion barrier layer having an upper surface and a lower surface and a central portion, and being formed from silicon, carbon, nitrogen and hydrogen with the nitrogen being non-uniformly distributed throughout the diffusion barrier layer. Thus, the nitrogen is more concentrated near the lower and upper surfaces of the diffusion barrier layer as compared to the central portion of the diffusion barrier layer. Methods for making the semiconductor devices are also provided.Type: GrantFiled: February 11, 2000Date of Patent: August 31, 2004Assignee: International Business Machines CorporationInventors: Stephan Alan Cohen, Timothy Joseph Dalton, John Anthony Fitzsimmons, Stephen McConnell Gates, Lynne M. Gignac, Paul Charles Jamison, Kang-Wook Lee, Sampath Purushothaman, Darryl D. Restaino, Eva Simonyi, Horatio Seymour Wildman
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Patent number: 6768111Abstract: A method of measurement of topographic features on a surface of a substrate is presented, wherein a focused beam of particles falls onto the surface of the substrate, and backscattered particles are detected with a particle detector. An opaque material is interposed between the surface and the detector, and the position of the shadow of an edge of the opaque material on the detector is recorded. The relative position of the edge and the surface of the substrate is then determined, and the topography of the surface determined as the particle beam and the substrate are moved with respect to one another.Type: GrantFiled: September 16, 2003Date of Patent: July 27, 2004Assignee: International Business Machines Corp.Inventors: Oliver C. Wells, Lynne M. Gignac, Jonathan L. Rullan, Conal E. Murray
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Publication number: 20040077140Abstract: A uniformly thick oxide film on a substrate is formed by using an anodization apparatus which deposits a blanket precursor film on a surface of a substrate; provides electrical contact to the precursor film; moves the precursor film into contact with an electrolyte solution such that substantially all electrically conductive surfaces, e.g., pin contacts, the substrate edge and a backside of the substrate are electrically isolated from the electrolyte; ensures that the surface of the precursor film on the substrate is in direct contact with the electrolyte solution; and which applies an anodizing current and/or voltage between the precursor film and a counter electrode so as to compensate for a voltage drop resulting from the presence of the electrolyte.Type: ApplicationFiled: October 16, 2002Publication date: April 22, 2004Inventors: Panayotis C. Andricacos, Roy Arthur Carruthers, Stephan Alan Cohen, John Michael Cotte, Lynne M. Gignac, Kenneth Jay Stein, Keith T. Kwietniak, Seshadri Subbanna, Horatio Seymour Wildman, David Earle Seeger, Andrew Herbert Simon
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Patent number: 6509265Abstract: A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.Type: GrantFiled: September 21, 2000Date of Patent: January 21, 2003Assignee: International Business Machines CorporationInventors: Patrick W. DeHaven, Anthony G. Domenicucci, Lynne M. Gignac, Glen L. Miles, Prabhat Tiwari, Yun-Yu Wang, Horatio S. Wildman, Kwong Hon Wong
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Publication number: 20020180046Abstract: A method for forming a conductive contact having an atomically flat interface. A layer containing titanium and one of cobalt, tungsten, tantalum, or molybdenum is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. A conductive material is deposited on top of the structure formed on anneal. A flat interface is formed that prevents diffusion of conductive materials into the underlying silicon substrate. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.Type: ApplicationFiled: June 5, 2001Publication date: December 5, 2002Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yun-Yu Wang, Cyril Cabral, Anthony G. Domenicucci, Johnathan Faltermeier, Lynne M. Gignac, Christian Lavoie, Colleen M. Snavely, Horatio S. Wildman, Kwong Hon Wong
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Patent number: 6417567Abstract: A conductive contact having an atomically flat interface. The contact includes, in order, a silicon substrate, a highly disordered silicide layer, and a titanium oxynitride layer. The silicide layer is formed of titanium, silicon, and one of the elements tungsten, tantalum, and molybdenum. The interface between the silicon substrate and the silicide layer is atomically flat. The flat interface prevents diffusion of conductive materials into the underlying silicon substrate. The contact is useful especially for very small devices and shallow junctions, such as are required for ULSI shallow junctions.Type: GrantFiled: January 13, 2000Date of Patent: July 9, 2002Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Lynne M. Gignac, Yun-Yu Wang, Horatio S. Wildman, Kwong Hon Wong, Roy A. Carruthers, Christian Lavoie, John A. Miller
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Publication number: 20020066673Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.Type: ApplicationFiled: January 22, 2002Publication date: June 6, 2002Applicant: International Business Machines CorporationInventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
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Patent number: 6344129Abstract: A method for plating copper conductors on an electronic substrate and devices formed are disclosed. In the method, an electroplating copper bath that is filled with an electroplating solution kept at a temperature between about 0° C. and about 18° C. is first provided. A copper layer on the electronic substrate immersed in the electroplating solution is then plated either in a single step or in a dual-step deposition process. The dual-step deposition process is more suitable for depositing copper conductors in features that have large aspect ratios, such as a via hole in a dual damascene structure having an aspect ratio of diameter/depth of more than ⅓ or as high as {fraction (1/10)}. Various electroplating parameters are utilized to provide a short resistance transient in either the single step deposition or the dual-step deposition process.Type: GrantFiled: October 13, 1999Date of Patent: February 5, 2002Assignee: International Business Machines CorporationInventors: Kenneth P. Rodbell, Panayotis C. Andricacos, Cyril Cabral, Jr., Lynne M. Gignac, Cyprian E. Uzoh, Peter S. Locke
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Patent number: 6180521Abstract: A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.Type: GrantFiled: January 6, 1999Date of Patent: January 30, 2001Assignee: International Business Machines CorporationInventors: Patrick W. DeHaven, Anthony G. Domenicucci, Lynne M. Gignac, Glen L. Miles, Prabhat Tiwari, Yun-Yu Wang, Horatio S. Wildman, Kwong Hon Wong
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Patent number: 6124639Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.Type: GrantFiled: July 1, 1999Date of Patent: September 26, 2000Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Lynne M. Gignac, Yun-Yu Wang, Horatio S. Wildman, Kwong Hon Wong
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Patent number: 6022801Abstract: A method for forming a conductive contact having an atomically flat interface is disclosed. A layer containing cobalt and titanium is deposited on a silicon substrate and the resulting structure annealed in a nitrogen containing atmosphere at about 500.degree. C. to about 700.degree. C. A conductive material is deposited on top of the structure formed on anneal. A flat interface, which prevents diffusion of conductive materials into the underlying silicon substrate is formed. The method can be used to form contacts for very small devices and shallow junctions, such as are required for ULSI shallow junctions.Type: GrantFiled: February 18, 1998Date of Patent: February 8, 2000Assignee: International Business Machines CorporationInventors: Anthony G. Domenicucci, Lynne M. Gignac, Yun-Yu Wang, Horatio S. Wildman, Kwong Hon Wong