Abstract: A capacitor structure for a memory element of an integrated circuit is provided. The capacitor is formed within a via hole defined through a first dielectric layer, and comprises a bottom electrode defined by an underlying conductive layer, and a capacitor dielectric filling the via with a dielectric barrier layer lining the via and separating the capacitor dielectric from the first dielectric layer. The capacitor dielectric is characterized by a material with high dielectric strength, preferably a ferroelectric material. An overlying conductive layer defines a top electrode contacting the capacitor dielectric. The barrier layer may comprise dielectric sidewall spacer formed within the via, or alternatively may comprise a region of mixed composition formed by interdiffusion of the first dielectric layer and the capacitor dielectric. The resulting capacitor structure is simple and compact, and may be fabricated with known CMOS, Bipolar or Bipolar-CMOS processes for submicron VLSI and ULSI integrated circuit.

Abstract: A method is provided for forming a capacitor structure for a memory element of an integrated circuit. The method comprises providing a first conductive electrode, forming a layer of a first dielectric material thereon, opening a via hole through the dielectric layer, providing within the via opening a capacitor dielectric having a higher dielectric strength than the first dielectric, the capacitor dielectric contacting the first electrode, planarizing the resulting structure and then forming a second conductive electrode thereon. Preferably, when the second dielectric comprises a ferroelectric dielectric material, sidewalls of the via opening are lined with a dielectric barrier layer to provide diffusion barrier between the ferroelectric and first dielectric layer. Advantageously, planarization is accomplished by chemical mechanical polishing to provide fully planar topography.