Abstract: A monolithically integrated amplifier comprising at least one heterojunction bipolar transistor and at least one field effect transistor is disclosed wherein the field effect transistor provides improved ruggedness by limiting the base and/or collector current to the HBT during severe load mismatch and/or high overdrive.

Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The in-phase and quadrature-phase signals may be normalized in-phase and quadrature-phase signals. Alternatively, a phase tracking subsystem may be provided that is responsive to the quadrature modulator to produce a phase signal that is responsive to phase changes in the modulated signal and that is independent of amplitude changes in the modulated signal.

Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Abstract: A thick layer of copper is formed on the outside the protective overcoat (PO) which protects an integrated circuit, and forms both an inductor and the upper electrode of a capacitor. Placing this layer outside the PO greatly reduces parasitic capacitances with the substrate in the devices.

Abstract: In one form of the invention, a circuit is disclosed, the circuit comprising: a transistor Q having an input terminal 14 with an avalanche breakdown voltage to electrical ground; and one or more diodes 16 arranged in a series between the input terminal 14 and electrical ground, the diode series 16 having a forward-biased voltage drop that is smaller than the avalanche breakdown voltage.

Abstract: Generally, and in one form of the invention a semiconductor device is presented comprising: a transistor comprising an emitter finger and a base finger; and a ballast impedance connected to the base finger. Other devices and methods are also disclosed.

Abstract: A monolithically realizable radio frequency (RF) bias choke implemented as a parallel inductor/capacitor arrangement connected between a DC supply node and an RF circuit bias point.

Abstract: A monolithically realizable harmonic trapping circuit that is a shunt connected series-resonant inductor-capacitor combination which has a resonant frequency designed to coincide with an undesired harmonic frequency of a desired fundamental frequency signal.