Patents by Inventor M. Sultan M. Siddiqui

M. Sultan M. Siddiqui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11532352
    Abstract: This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the virtual ground, a second transistor coupled to at least the first data storage line and the first transistor, a third transistor coupled to at least the second data storage line and the read word line, and a fourth transistor coupled at least the first data storage line and the read word line.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: December 20, 2022
    Assignee: SYNOPSYS, INC.
    Inventors: M. Sultan M. Siddiqui, Sudhir Kumar Sharma, Sudhir Kumar, Ravindra Kumar Shrivastava
  • Patent number: 11062766
    Abstract: A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS transistor) to reduce data-dependent current leakage from a read bitline. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bitline. For example, a weak NMOS keeper that includes a sense amplifier, an inverter, and an NMOS connected to supply voltage VDD provides a path between the read bitline and VDD through the weak NMOS keeper.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: July 13, 2021
    Assignee: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Sudhir Kumar Sharma, Saurabh Porwal, Khatik Bhagvan Pannalal, Sudhir Kumar
  • Publication number: 20210090639
    Abstract: This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the virtual ground, a second transistor coupled to at least the first data storage line and the first transistor, a third transistor coupled to at least the second data storage line and the read word line, and a fourth transistor coupled at least the first data storage line and the read word line.
    Type: Application
    Filed: September 18, 2020
    Publication date: March 25, 2021
    Applicant: Synopsys, Inc.
    Inventors: M. Sultan M. SIDDIQUI, Sudhir Kumar SHARMA, Sudhir KUMAR, Ravindra Kumar SHRIVASTAVA
  • Publication number: 20200219558
    Abstract: A structure for an integrated circuit is disclosed for storing data. The integrated circuit includes a memory cell array of bit cells configured in a static random access memory (SRAM) architecture. The memory cell array is coupled to wordlines arranged in rows that control operations such as Read and Write operations. To enhance the read sensing margin of the SRAM configuration, the read port of a bit cell may include a wordline that drives two transistors (e.g., a PMOS and an NMOS transistor) to reduce data-dependent current leakage from a read bitline. An additional weak transistor keeper configuration may be used in the integrated circuit to compensate for current leakage from the read bitline. For example, a weak NMOS keeper that includes a sense amplifier, an inverter, and an NMOS connected to supply voltage VDD provides a path between the read bitline and VDD through the weak NMOS keeper.
    Type: Application
    Filed: January 3, 2020
    Publication date: July 9, 2020
    Inventors: M. Sultan M. Siddiqui, Sudhir Kumar Sharma, Saurabh Porwal, Khatik Bhagvan Pannalal, Sudhir Kumar
  • Patent number: 10510402
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar
  • Publication number: 20190130965
    Abstract: The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.
    Type: Application
    Filed: October 25, 2018
    Publication date: May 2, 2019
    Applicant: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Sumit Srivastav, Dattatray Ramrao Wanjul, Manankumar Suthar, Sudhir Kumar
  • Patent number: 9842642
    Abstract: An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC1, . . . , BCn) comprising a first and a second one of the bit cells (BC1, BC2) having a static random access memory architecture. The first and the second bit cells (BC1, BC2) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C1, C2) of the memory cell array (100). During a write access to the first bit cell (BC1), the first bit cell (BC1) undergoes a write operation, whereas the second bit cell (BC2) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: December 12, 2017
    Assignee: Synopsys, Inc.
    Inventors: M. Sultan M. Siddiqui, Shailendra Sharad, Hemant Vats, Amit Khanuja