Patents by Inventor Maciej Wojnowski

Maciej Wojnowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150177373
    Abstract: A wireless communication system includes a first semiconductor module and a second semiconductor module. The first semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the first semiconductor module and the antenna structure of the first semiconductor module are arranged within a common package. The semiconductor die of the first semiconductor module includes a transmitter module configured to transmit the wireless communication signal through the antenna structure of the first semiconductor module. The second semiconductor module includes a semiconductor die connected to an antenna structure. The semiconductor die of the second semiconductor module includes a receiver module configured to receive the wireless communication signal through the antenna structure of the second semiconductor module from the first semiconductor module.
    Type: Application
    Filed: December 19, 2013
    Publication date: June 25, 2015
    Inventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Walter Hartner
  • Patent number: 9064787
    Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: June 23, 2015
    Assignee: Infineon Technologies AG
    Inventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Thorsten Meyer
  • Publication number: 20150171033
    Abstract: A semiconductor device package includes an encapsulant and a semiconductor chip. The semiconductor chip is at least partly embedded in the encapsulant. A microwave component including at least one electrically conducting wall structure is integrated in the encapsulant. Further, the semiconductor device package includes an electrical interconnect configured to electrically couple the microwave component to the semiconductor chip.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 18, 2015
    Inventors: Ernst Seler, Maciej Wojnowski, Walter Hartner, Josef Boeck
  • Publication number: 20150117862
    Abstract: According to an embodiment, a circuit board includes a signal line including at least portion of a first conductive layer that has a first portion extending over a cavity in the circuit board from a first side of the cavity. The circuit board also includes a first plurality of conductive vias surrounding the cavity and the first plurality of vias include at least one blind via disposed adjacent to the first side of the cavity.
    Type: Application
    Filed: October 30, 2013
    Publication date: April 30, 2015
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Saverio Trotta, Jagjit Singh Bal, Maciej Wojnowski, Ernst Seler, Mehran Pour Mousavi
  • Publication number: 20150061091
    Abstract: An electronic device which comprises at least one interconnect, a semiconductor chip comprising at least one electric chip pad, an encapsulant structure packaging at least a part of the semiconductor chip, and an electrically conductive redistribution layer arranged between and electrically coupled with the at least one interconnect and the at least one chip pad, wherein the redistribution layer comprises at least one adjustment structure configured for adjusting radio frequency properties of a transition between the semiconductor chip and its periphery.
    Type: Application
    Filed: August 31, 2013
    Publication date: March 5, 2015
    Applicant: Infineon Technologies AG
    Inventors: Ernst SELER, Maciej Wojnowski
  • Patent number: 8952521
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: February 10, 2015
    Assignee: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Patent number: 8866292
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: October 21, 2014
    Assignee: Infineon Technologies AG
    Inventors: Gottfried Beer, Maciej Wojnowski, Mehran Pour Mousavi
  • Publication number: 20140117515
    Abstract: A semiconductor module comprises a wafer package comprising an integrated circuit (IC) device embedded within the wafer package and a layer comprising at least one antenna structure and redistribution structures, wherein the antenna structure is coupled to the IC device and wherein the redistribution structures are coupled to the IC device.
    Type: Application
    Filed: January 6, 2014
    Publication date: May 1, 2014
    Applicant: Infineon Technologies AG
    Inventors: Rudolf LACHNER, Linus MAURER, Maciej WOJNOWSKI
  • Publication number: 20140110840
    Abstract: In one embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A chip is disposed in the substrate. The chip includes a plurality of contact pads at the first major surface. A first antenna structure is disposed at the first major surface. A reflector is disposed at the second major surface.
    Type: Application
    Filed: January 8, 2013
    Publication date: April 24, 2014
    Applicant: Infineon Technologies AG
    Inventors: Maciej Wojnowski, Walter Hartner, Ottmar Geitner, Gottfried Beer, Klaus Pressel, Mehran Pour Mousavi
  • Publication number: 20140110841
    Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a substrate having a first major surface and an opposite second major surface. A first chip is disposed in the substrate. The first chip includes a plurality of contact pads at the first major surface. A via bar is disposed in the substrate. An antenna structure is disposed within the via bar.
    Type: Application
    Filed: January 8, 2013
    Publication date: April 24, 2014
    Applicant: Infineon Technologies AG
    Inventors: Gottfried Beer, Maciej Wojnowski, Mehran Pour Mousavi
  • Patent number: 8669655
    Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 11, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ottmar Geitner, Walter Hartner, Maciej Wojnowski, Ulrich Wachter, Michael Bauer, Andreas Stueckjuergen
  • Publication number: 20140035154
    Abstract: A chip package is provided, the chip package including: a chip including at least one contact pad formed on a chip front side; an encapsulation material at least partially surrounding the chip and covering the at least one contact pad; and at least one electrical interconnect formed through the encapsulation material, wherein the at least one electrical interconnect is configured to electrically redirect the at least one contact pad from a chip package first side at the chip front side to at least one solder structure formed over a chip package second side at a chip back side.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Applicant: Infineon Technologies AG
    Inventors: Ottmar Geitner, Walter Hartner, Maciej Wojnowski, Ulrich Wachter, Michael Bauer, Andreas Stueckjuergen
  • Patent number: 8624381
    Abstract: A semiconductor module, comprises a package molding compound layer comprising an integrated circuit (IC) device embedded within a package molding compound, the integrated circuit device and the package molding compound having a common surface. Structures are formed to connect the semiconductor module to an external board, the structures electrically connected to the integrated circuit device. A layer is formed on the common surface, the layer comprising at least one integrated antenna structure, the integrated antenna structure being coupled to the IC device.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: January 7, 2014
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Publication number: 20130241059
    Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein. The semiconductor module has a bonding interconnect structure that connects an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.
    Type: Application
    Filed: April 23, 2013
    Publication date: September 19, 2013
    Applicant: Infineon Technologies AG
    Inventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Thorsten Meyer
  • Patent number: 8460967
    Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
    Type: Grant
    Filed: September 18, 2012
    Date of Patent: June 11, 2013
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Patent number: 8451618
    Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: May 28, 2013
    Assignee: Infineon Technologies AG
    Inventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Thorsten Meyer
  • Patent number: 8278749
    Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: October 2, 2012
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski
  • Publication number: 20120104574
    Abstract: A semiconductor module having one or more integrated antennas in a single package is provided herein to comprise a bonding interconnect structure having a plurality of individual bonding elements that are confined to a relatively small area of the bottom of a package. In particular, the semiconductor module comprises a bonding interconnect structure configured to connect an integrated package to a printed circuit board (PCB), wherein the integrated antenna structures are located at greater center-to-center distance from the IC device than the three dimensional interconnect structures. Therefore, the bonding interconnect structures are confined to a connection area that causes a part of the package containing the one or more antenna structures to extend beyond the bonding interconnect structure as a cantilevered structure. Such a bonding interconnect structure result in a package that is in contact with a PCB at a relatively small area that supports the load of the package.
    Type: Application
    Filed: October 28, 2010
    Publication date: May 3, 2012
    Applicant: Infineon Technologies AG
    Inventors: Josef Boeck, Rudolf Lachner, Maciej Wojnowski, Thorsten Meyer
  • Publication number: 20100193935
    Abstract: A semiconductor module comprises components in one wafer level package. The module comprises an integrated circuit (IC) chip embedded within a package molding compound. The package comprises a molding compound package layer coupled to an interface layer for integrating an antenna structure and a bonding interconnect structure to the IC chip. The bonding interconnect structure comprises three dimensional interconnects. The antenna structure and bonding interconnect structure are coupled to the IC chip and integrated within the interface layer in the same wafer fabrication process.
    Type: Application
    Filed: December 23, 2009
    Publication date: August 5, 2010
    Applicant: Infineon Technologies AG
    Inventors: Rudolf Lachner, Linus Maurer, Maciej Wojnowski