Patents by Inventor Madhu Chidurala

Madhu Chidurala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11257740
    Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: February 22, 2022
    Assignee: WOLFSPEED, INC.
    Inventors: Alexander Komposch, Simon Ward, Madhu Chidurala
  • Patent number: 11228287
    Abstract: An electronic package houses one or more RF amplifier circuits. At least one of an input or output impedance matching network integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an amplifier circuit, includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the amplifier circuit at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching circuits may be shared, and may be connected anywhere along the multi-stage decoupling network.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: January 18, 2022
    Assignee: Cree, Inc.
    Inventors: Madhu Chidurala, Marvin Marbell, Niklas Thulin
  • Publication number: 20210408978
    Abstract: A packaged radio frequency transistor amplifier includes a package housing, an RF transistor amplifier die that is mounted within the package housing, a first capacitor die that is mounted within the package housing, an input leadframe that extends through the package housing to electrically connect to a gate terminal of the RF transistor amplifier die, and an output leadframe that extends through the package housing to electrically connect to a drain terminal of the RF transistor amplifier die. The output leadframe includes an output pad region, an output lead that extends outside of the package housing, and a first arm that extends from one of the output pad region and the output lead to be adjacent the first capacitor die.
    Type: Application
    Filed: June 24, 2020
    Publication date: December 30, 2021
    Inventors: Madhu Chidurala, Richard Wilson, Haedong Jang, Simon Ward
  • Publication number: 20210408977
    Abstract: Inductance-capacitance (LC) resonators having different resonant frequencies, and radio frequency (RF) transistor amplifiers including the same. One usage of such LC resonators is to implement RF short/DC block circuits. A RF transistor amplifier may include a transistor on a base of the RF transistor amplifier coupled to an input and an output of the RF transistor amplifier; a first inductance-capacitance (LC) resonator comprising a first inductance and a first capacitance; and a second LC resonator comprising a second inductance and a second capacitance. The first LC resonator may be configured to resonate at a first frequency, and the second LC resonator may be configured to resonate at a second frequency different from the first frequency.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Inventors: Haedong Jang, Madhu Chidurala, Richard Wilson
  • Publication number: 20210399692
    Abstract: An electronic package houses one or more RF amplifier circuits. At least one of an input or output impedance matching network integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an amplifier circuit, includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the amplifier circuit at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching circuits may be shared, and may be connected anywhere along the multi-stage decoupling network.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 23, 2021
    Inventors: Madhu Chidurala, Marvin Marbell, Niklas Thulin
  • Patent number: 11201591
    Abstract: In an asymmetric Doherty amplifier circuit, one or more shunt reactive components are added to at least one side of an impedance inverter connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers caused by their different parasitic capacitances. This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter. In one embodiment, a shunt inductance is connected between the impedance inverter, on the side of the larger amplifier, and RF signal ground. The inductance is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier. In another embodiment, a shunt capacitor is connected on the side of the smaller amplifier, thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: December 14, 2021
    Assignee: Cree, Inc.
    Inventors: Haedong Jang, Sonoko Aristud, Marvin Marbell, Madhu Chidurala
  • Publication number: 20210313283
    Abstract: A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.
    Type: Application
    Filed: September 24, 2020
    Publication date: October 7, 2021
    Inventors: Richard Wilson, Madhu Chidurala
  • Publication number: 20210280478
    Abstract: A radio frequency (RF) package includes a support having a semiconductor die attach region; a frame that includes an electrically insulative member having a lower side attached to the support and an upper side opposite the support; the frame includes an opening at least partially registered with said semiconductor die attach region; and the frame includes an upper metallization at the upper side of the electrically insulative member and a lower metallization The frame includes first electrically conductive edge connection connecting the first metallization to the first lower metallization.
    Type: Application
    Filed: March 6, 2020
    Publication date: September 9, 2021
    Inventors: Richard Wilson, Haedong Jang, Simon Ward, Madhu Chidurala
  • Publication number: 20210265249
    Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Alexander Komposch, Simon Ward, Madhu Chidurala
  • Patent number: 11031913
    Abstract: In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 8, 2021
    Assignee: Cree, Inc.
    Inventors: Madhu Chidurala, Marvin Marbell, Simon Ward
  • Publication number: 20200366249
    Abstract: In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.
    Type: Application
    Filed: May 17, 2019
    Publication date: November 19, 2020
    Inventors: Madhu Chidurala, Marvin Marbell, Simon Ward
  • Publication number: 20200304074
    Abstract: In an asymmetric Doherty amplifier circuit, one or more shunt reactive components are added to at least one side of an impedance inverter connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers caused by their different parasitic capacitances. This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter. In one embodiment, a shunt inductance is connected between the impedance inverter, on the side of the larger amplifier, and RF signal ground. The inductance is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier. In another embodiment, a shunt capacitor is connected on the side of the smaller amplifier, thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier.
    Type: Application
    Filed: March 20, 2019
    Publication date: September 24, 2020
    Inventors: Haedong Jang, Sonoko Aristud, Marvin Marbell, Madhu Chidurala