Patents by Inventor Madhur Bobde

Madhur Bobde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220262898
    Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.
    Type: Application
    Filed: May 4, 2022
    Publication date: August 18, 2022
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Bum-Seok Suh
  • Patent number: 11417648
    Abstract: An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: August 16, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Bum-Seok Suh, Madhur Bobde, Zhiqiang Niu, Junho Lee, Xiaojing Xu, Zhaorong Zhuang
  • Publication number: 20220208724
    Abstract: A semi-wafer level packaging method comprises the steps of providing a wafer; grinding a back side of the wafer; forming a metallization layer; removing a peripheral ring; bonding a first tape; applying a dicing process; bonding a second tape; removing the first tape; bonding a supporting structure; bonding a third tape; removing the second tape; and applying a singulation process. A semi-wafer level packaging method comprises the steps of providing a wafer; attaching a carrier wafer to the wafer; grinding a back side of the wafer; forming a metallization layer; applying a dicing process; bonding a supporting structure; removing the carrier wafer; bonding a tape; and applying a singulation process.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Yan Xun Xue, Madhur Bobde, Long-Ching Wang, Bo Chen
  • Patent number: 11342410
    Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: May 24, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Bum-Seok Suh
  • Patent number: 11245016
    Abstract: A semiconductor apparatus has a silicon carbide substrate heavily doped with the first conductivity type and a lightly doped silicon carbide drift region of the first conductivity type over the silicon carbide substrate. A first body region in the drift region is doped with second conductivity type opposite the first. A first source region in the first body region is heavily doped with the first conductivity type. A gate trench is formed in the first source region and first body region. At least one sidewall of the gate trench is parallel to a crystal plane of the silicon carbide structure having greater carrier mobility than a C-face thereof. The gate trench extends a length of the first body region and the source region to a separation region laterally adjacent to the first region wherein the separation region is in the drift region.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 8, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: David Sheridan, Vipindas Pala, Madhur Bobde
  • Publication number: 20210305406
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Application
    Filed: June 13, 2021
    Publication date: September 30, 2021
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Publication number: 20210273046
    Abstract: A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile includes multiple doped regions with peak doping levels where a first doped region adjacent to a first side of the field stop zone has a first peak doping level that is not higher than a last peak doping level of a last doped region adjacent to the base region. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.
    Type: Application
    Filed: May 4, 2021
    Publication date: September 2, 2021
    Inventors: Lei Zhang, Karthik Padmanabhan, Lingpeng Guan, Jian Wang, Lingbing Chen, Wim Aarts, Hongyong Xue, Wenjun Li, Madhur Bobde
  • Publication number: 20210257461
    Abstract: A method for forming a superjunction power semiconductor device includes forming multiple epitaxial layers of a first conductivity type on a semiconductor substrate and implanting dopants of a second conductivity type into each epitaxial layer to form a first group of implanted regions in a first region and a second group of implanted regions in a second region in each epitaxial layer. The multiple epitaxial layers are annealed to form multiple columns of the second conductivity type having slanted sidewalls across the first to last epitaxial layers. The columns include a first group of columns formed by the implanted regions of the first group and having a first grading and a second group of columns formed by the implanted regions of the second group and having a second grading, where the second grading is less than the first grading.
    Type: Application
    Filed: May 6, 2021
    Publication date: August 19, 2021
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Publication number: 20210242319
    Abstract: A semiconductor apparatus has a silicon carbide substrate heavily doped with the first conductivity type and a lightly doped silicon carbide drift region of the first conductivity type over the silicon carbide substrate. A first body region in the drift region is doped with second conductivity type opposite the first. A first source region in the first body region is heavily doped with the first conductivity type. A gate trench is formed in the first source region and first body region. At least one sidewall of the gate trench is parallel to a crystal plane of the silicon carbide structure having greater carrier mobility than a C-face thereof. The gate trench extends a length of the first body region and the source region to a separation region laterally adjacent to the first region wherein the separation region is in the drift region.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 5, 2021
    Inventors: David Sheridan, Vipindas Pala, Madhur Bobde
  • Patent number: 11038022
    Abstract: A superjunction power semiconductor device includes a termination region with superjunction structures having higher breakdown voltage than the breakdown voltage of the active cell region. In one embodiment, the termination region includes superjunction structures having lower column charge as compared to the superjunction structures formed in the active cell region. In other embodiments, a superjunction power semiconductor device incorporating superjunction structures with slanted sidewalls where the grading of the superjunction columns in the termination region is reduced as compared to the column grading in the active cell region. The power semiconductor device is made more robust by ensuring any breakdown occurs in the core region as opposed to the termination region. Furthermore, the manufacturing process window for the power semiconductor device is enhanced to improve the manufacturing yield of the power semiconductor device.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Madhur Bobde, Karthik Padmanabhan, Lingpeng Guan
  • Patent number: 11038037
    Abstract: A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: June 15, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Anup Bhalla, Hamza Yilmaz
  • Patent number: 11031465
    Abstract: A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile formed in the field stop zone includes varying, non-constant doping levels. In some embodiments, the enhanced doping profile includes one of an extended graded doping profile, a multiple stepped flat doping profile, or a multiple spike doping profile. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: June 8, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Lei Zhang, Karthik Padmanabhan, Lingpeng Guan, Jian Wang, Lingbing Chen, Wim Aarts, Hongyong Xue, Wenjun Li, Madhur Bobde
  • Patent number: 10998264
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 4, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Publication number: 20210125940
    Abstract: A semiconductor package comprises a semiconductor substrate, a first metal layer, an adhesive layer, a second metal layer, a rigid supporting layer, and a plurality of contact pads. A thickness of the semiconductor substrate is equal to or less than 50 microns. A thickness of the rigid supporting layer is larger than the thickness of the semiconductor substrate. A thickness of the second metal layer is larger than a thickness of the first metal layer. A method comprises the steps of providing a device wafer; providing a supporting wafer; attaching the supporting wafer to the device wafer via an adhesive layer; and applying a singulation process so as to form a plurality of semiconductor packages.
    Type: Application
    Filed: December 30, 2020
    Publication date: April 29, 2021
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Jun Lu, Long-Ching Wang, Madhur Bobde, Bo Chen, Shuhua Zhou
  • Patent number: 10991680
    Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: April 27, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Madhur Bobde, Xiaobin Wang, Lin Chen
  • Publication number: 20210098569
    Abstract: An apparatus comprising an insulated gate bipolar transistor and a super junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor and the super-junction metal-oxide semiconductor field effect transistor are electrically and optionally structurally coupled.
    Type: Application
    Filed: September 27, 2019
    Publication date: April 1, 2021
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Bum-Seok Suh
  • Publication number: 20210098448
    Abstract: An intelligent power module (IPM) comprises a first, second, third and fourth die supporting elements, a first group of insulated gate bipolar transistors (IGBTs), a second group of IGBTs, a first group of super-junction metal-oxide-semiconductor field-effect transistors (MOSFETs), a second group of super-junction MOSFETs, a fifth die supporting element, a low voltage IC, a high voltage IC, and a molding encapsulation. The low and high voltage ICs are attached to the fifth die supporting element. The molding encapsulation encloses the first, second, third and fourth die supporting elements, the first group of IGBTs, the second group of IGBTs, the first group of super-junction MOSFETs, the second group of super-junction MOSFETs, the fifth die supporting element, the low voltage IC, the high voltage IC.
    Type: Application
    Filed: November 9, 2020
    Publication date: April 1, 2021
    Applicant: ALPHA AND OMEGA SEMICONDUCTOR INTERNATIONAL LP
    Inventors: Bum-Seok Suh, Madhur Bobde, Zhiqiang Niu, Junho Lee, Xiaojing Xu, Zhaorong Zhuang
  • Publication number: 20210083088
    Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 18, 2021
    Applicant: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Long-Ching Wang, Madhur Bobde, Xiaobin Wang, Lin Chen
  • Patent number: 10931276
    Abstract: An apparatus comprising an insulated gate bipolar transistor; and a super-junction metal-oxide semiconductor field effect transistor wherein the insulated gate bipolar transistor wherein the super-junction metal-oxide semiconductor field effect transistor are structurally coupled and wherein the super-junction metal-oxide semiconductor field effect transistor is configured to switch to an ‘on’ state from an ‘off’ state and an ‘off’ state from an ‘on’ state.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 23, 2021
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Bum-Seok Suh, Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan
  • Publication number: 20210020567
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz