Patents by Inventor Madhur Bobde

Madhur Bobde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180254342
    Abstract: A method for forming a lateral superjunction MOSFET device includes forming a semiconductor body including a lateral superjunction structure and a first column connected to the lateral superjunction structure. The MOSFET device includes the first column to receive current from the channel when the MOSFET is turned on and to distribute the channel current to the lateral superjunction structure functioning as the drain drift region. In some embodiment, the MOSFET device includes a second column disposed in close proximity to the first column. The second column disposed near the first column is used to pinch off the first column when the MOSFET device is to be turned off and to block the high voltage being sustained by the MOSFET device at the drain terminal from reaching the gate structure. In some embodiments, the MOSFET device further includes termination structures for the drain, source and body contact doped region fingers.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 6, 2018
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
  • Patent number: 10050134
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: August 14, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 10038062
    Abstract: A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of substrate. Deep trenches are provided for isolation between multi-channel VTVS. Trench gates are also provided for increasing the capacitance of VTVS with integrated EMI filter.
    Type: Grant
    Filed: August 20, 2017
    Date of Patent: July 31, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Shekar Mallikarjunaswamy, Madhur Bobde
  • Publication number: 20180212048
    Abstract: A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.
    Type: Application
    Filed: July 25, 2017
    Publication date: July 26, 2018
    Inventors: Wenjie Zhang, Madhur Bobde, Qufei Chen, Kyle Terrill
  • Publication number: 20180212022
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 26, 2018
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Patent number: 10032728
    Abstract: A trench-type metal-oxide-semiconductor field-effect transistor (MOSFET) device and a fabrication method are disclosed. The trench MOSFET device comprises a semiconductor substrate of a first conductivity type. The semiconductor substrate has a plurality of first trenches arranged side by side in a first preset area of the semiconductor substrate extending along a first direction and a plurality of second trenches arranged side by side in a second preset area of the semiconductor substrate extending along a second direction perpendicular to the first direction. A control gate is formed in each of the pluralities of first and second trenches. A body region of a second conductivity type is formed at a top portion of the semiconductor substrate near sidewalls of the pluralities of first and second trenches. A source region of the first conductivity type is formed on a top portion of the body region.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 24, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Xiaobin Wang, Madhur Bobde, Paul Thorup
  • Patent number: 10032861
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
    Type: Grant
    Filed: September 30, 2017
    Date of Patent: July 24, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Hamza Yilmaz, Madhur Bobde
  • Publication number: 20180204937
    Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 19, 2018
    Inventors: Anup Bhalla, Madhur Bobde, Yongping Ding, Xiaotian Zhang, Yueh-Se Ho
  • Patent number: 9997593
    Abstract: A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench type power semiconductor device includes a first contact hole formed in a mesa in the active area and a second contact hole formed in a mesa in an active to termination intermediate area, where the first contact hole is deeper and wider than the second contact hole. The method comprises the steps of providing a semiconductor substrate, etching an epitaxial layer, depositing a conductive material, depositing an insulation passivation layer and etching through the insulation passivation layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: June 12, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: Yongping Ding, Hamza Yilmaz, Xiaobin Wang, Madhur Bobde
  • Patent number: 9991380
    Abstract: A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a conductive gate finger, a source region finger, a body contact region finger and a drain region finger arranged laterally within each transistor cell. Each of the drain region fingers, the source region fingers and the body contact region fingers is a doped region finger having a termination region at an end of the doped region finger. The lateral superjunction MOSFET device further includes a termination structure formed in the termination region of each doped region finger and including one or more termination columns having the same conductivity type as the doped region finger and positioned near the end of the doped region finger. The one or more termination columns extend through the lateral superjunction structure and are electrically unbiased.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: June 5, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Lingpeng Guan, Karthik Padmanabhan, Hamza Yilmaz
  • Patent number: 9978740
    Abstract: A unidirectional transient voltage suppressor (TVS) device is formed with first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 22, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Publication number: 20180082993
    Abstract: A transient-voltage suppressing (TVS) device disposed on a semiconductor substrate including a low-side steering diode, a high-side steering diode integrated with a main Zener diode for suppressing a transient voltage. The low-side steering diode and the high-side steering diode integrated with the Zener diode are disposed in the semiconductor substrate and each constituting a vertical PN junction as vertical diodes in the semiconductor substrate whereby reducing a lateral area occupied by the TVS device. In an exemplary embodiment, the high-side steering diode and the Zener diode are vertically overlapped with each other for further reducing lateral areas occupied by the TVS device.
    Type: Application
    Filed: September 30, 2017
    Publication date: March 22, 2018
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventor: Madhur Bobde
  • Patent number: 9911728
    Abstract: A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A set of source regions is formed within a top surface of the second epitaxial layer. Implant regions are formed in the second epitaxial layer, with a first implant region located below the first source region.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: March 6, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ning Shi, Lingpeng Guan, Madhur Bobde
  • Patent number: 9882049
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: January 30, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: François Hébert, Madhur Bobde, Anup Bhalla
  • Publication number: 20180026094
    Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
    Type: Application
    Filed: September 30, 2017
    Publication date: January 25, 2018
    Inventors: Hamza Yilmaz, Madhur Bobde
  • Publication number: 20180026025
    Abstract: A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.
    Type: Application
    Filed: September 30, 2017
    Publication date: January 25, 2018
    Applicant: Alpha and Omega Semiconductor Incorporated
    Inventors: MADHUR BOBDE, WENJIANG ZENG, LIMIN WENG
  • Patent number: 9876096
    Abstract: A plurality of gate trenches is formed into an epitaxial region of a first conductivity type over a semiconductor substrate. One or more contact trenches are formed into the epitaxial region, each between two adjacent gate trenches. One or more source regions of the first conductivity type are formed in a top portion of the epitaxial region between a contact trench and a gate trench. A barrier metal is formed inside each contact trench. Each gate trench is substantially filled with a conductive material separated from trench walls by a layer of dielectric material to form a gate . A heavily doped well region of a conductivity opposite the first type is provided in the epitaxial region proximate a bottom portion of each of the contact trenches. A horizontal width of a gap between the well region and the gate trench is about 0.05 ?m to 0.2 ?m.
    Type: Grant
    Filed: October 27, 2016
    Date of Patent: January 23, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Madhur Bobde, Sik Lui, Hamza Yilmaz, Jongoh Kim, Daniel Ng
  • Patent number: 9876073
    Abstract: This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: January 23, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Anup Bhalla, Madhur Bobde, Tinggang Zhu
  • Patent number: 9865694
    Abstract: A plurality of gate trenches is formed into a semiconductor substrate in an active cell region. One or more other trenches are formed in a different region. Each gate trench has a first conductive material in lower portions and a second conductive material in upper portions. In the gate trenches, a first insulating layer separates the first conductive material from the substrate, a second insulating layer separates the second conductive material from the substrate and a third insulating material separates the first and second conductive materials. The other trenches contain part of the first conductive material in a half-U shape in lower portions and part of the second conductive material in upper portions. In the other trenches, the third insulating layer separates the first and second conductive materials. The first insulating layer is thicker than the third insulating layer, and the third insulating layer is thicker than the second.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: January 9, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Yeeheng Lee, Lingpeng Guan, Hongyong Xue, Yiming Gu, Yang Xiang, Terence Huang, Sekar Ramamoorthy, Wenjun Li, Hong Chang, Madhur Bobde, Paul Thorup, Hamza Yilmaz
  • Patent number: 9865678
    Abstract: A semiconductor device includes a semiconductor substrate and epitaxial layer of a first conductivity type with the epitaxial layer on a top surface of the substrate. A body region of a second conductivity type opposite the first conductivity type is disposed near a top surface of the epitaxial layer. A first conductivity type source region is inside the body region and a drain is at a bottom surface of the substrate. An inslated gate overlaps the source and body regions. First and second trenches in the epitaxial layer are lined with insulation material and filled with electrically conductive material. Second conductivity type buried regions are positioned below the trenches. Second conductivity type charge linking paths along one or more walls of the first trench electrically connect a first buried region to the body region. A second buried region is separated from the body region by portions of the expitaxial layer.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: January 9, 2018
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Anup Bhalla, Hamza Yilmaz, Madhur Bobde, Lingpeng Guan, Jun Hu, Jongoh Kim, Yongping Ding