Abstract: Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory array includes a plurality of memory cells to store data bits. Each of the plurality of memory cells includes a transistor having drain, source, and gate terminals, and a plurality of program nodes, each of the program nodes charged to a predetermined voltage and coupled to a respective one of a plurality of bit lines. For each memory cell in a subset of the plurality of memory cells, none of the plurality of program nodes is coupled to the drain terminal of the transistor to program the each memory cell in the subset of the plurality of memory cells to store at least one data bit, the at least one data bit is most occurred between the data bits.

Abstract: A tri-state sense amplifier is provided, which includes an enable input, a latch and an output driver. The latch has first and second complementary inputs and first and second complementary latch outputs, which are gated by the enable input. The output driver includes a data output, a pull-up transistor coupled to the data output and having a control terminal coupled to the first latch output, and a pull-down transistor coupled to the data output and having a control terminal coupled to the second latch output.

Abstract: A plurality of single transistor memory cells arrayed in columns with the memory cells within a column connected to one or the other of precharged first and second output lines. An input line connected to the gate of the single transistor causes the first output line to be pulled to a first voltage when the cell is programmed a "true" and to be pulled to a second voltage when the cell is programmed a "complement". A pair of cross-coupled transistors connected between the first and second output lines of a column cause the second output line to be maintained at the precharged voltage when programmed a "true" and causes the first output line to be maintained at a precharged voltage when programmed a "complement".