Patents by Inventor Makoto Fujiwara

Makoto Fujiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11289148
    Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: March 29, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Makoto Fujiwara
  • Publication number: 20210349981
    Abstract: An authentication method is used by an automated driving system that includes a vehicle and an external device, the external device communicating with the vehicle to cause the vehicle to implement automated driving. The vehicle holds a first certificate that certifies validity of the vehicle. The external device holds a second certificate that certifies validity of the external device. The authentication method includes: validating a third certificate that certifies validity of a combination of the vehicle and the external device, in accordance with a result of device authentication performed between the vehicle and the external device by reference to the first certificate and the second certificate.
    Type: Application
    Filed: July 21, 2021
    Publication date: November 11, 2021
    Applicant: Panasonic Intellectual Property Corporation of America
    Inventors: Yoshihiro UJIIE, Hideki MATSUSHIMA, Makoto FUJIWARA
  • Publication number: 20210285516
    Abstract: A seal chain includes two inner link plates opposed to and spaced apart from each other, a tubular bushing, opposite ends of the bushing being respectively joined to the two inner link plates, a pin rotationally inserted into the bushing, a tubular roller into which the bushing is inserted, the roller being rotationally supported by the bushing, and two outer link plates arranged to externally hold the two inner link plates in between, opposite ends of the pin being respectively joined to the two outer link plates. A recess into which an end of the roller is inserted is formed in an inner surface of each of the inner link plates.
    Type: Application
    Filed: October 3, 2017
    Publication date: September 16, 2021
    Applicant: TSUBAKIMOTO CHAIN CO.
    Inventors: Takuya Yasu, Makoto Fujiwara, Yusuke Nishizawa
  • Publication number: 20210090632
    Abstract: A memory control apparatus controls access to a DRAM having a plurality of banks. The apparatus comprises a first generating unit configured to generate an access command in accordance with an access request for the DRAM and store the access command in a buffer; a second generating unit configured to generate a bank-designated refresh request for the DRAM; and an issuing unit configured to issue a DRAM command to the DRAM based on an access command stored in the buffer and a refresh request generated by the second generating unit. The second generating unit determines a bank for which the refresh request is generated, based on an access time for each bank of the DRAM by not less than one access command stored in the buffer.
    Type: Application
    Filed: September 16, 2020
    Publication date: March 25, 2021
    Inventor: Makoto Fujiwara
  • Patent number: 10742675
    Abstract: Provided is a fraudulent message detection device that detects a fraudulent message in a bus network and includes: a resynchronization detector that detects an edge of a signal on a bus in the bus network and determines whether to perform resynchronization, so as to adjust a sampling point in a one-bit period; a transmission and receiving control unit that obtains a first logical value and a second logical value in a one-bit period after the resynchronization detector determines to perform the resynchronization, the first logical value being a logical value at a sampling point used before the edge is detected, the second logical value being a logical value at a sampling point after the resynchronization is performed; a comparator that compares the first and second logical values; and a fraud detection processing unit that executes post-fraud-detection processing, when the first and second logical values do not coincide.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 11, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventor: Makoto Fujiwara
  • Patent number: 10269821
    Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 23, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Masao Shingu, Katsuyuki Sekine, Hirokazu Ishigaki, Makoto Fujiwara
  • Publication number: 20180316710
    Abstract: Provided is a fraudulent message detection device that detects a fraudulent message in a bus network and includes: a resynchronization detector that detects an edge of a signal on a bus in the bus network and determines whether to perform resynchronization, so as to adjust a sampling point in a one-bit period; a transmission and receiving control unit that obtains a first logical value and a second logical value in a one-bit period after the resynchronization detector determines to perform the resynchronization, the first logical value being a logical value at a sampling point used before the edge is detected, the second logical value being a logical value at a sampling point after the resynchronization is performed; a comparator that compares the first and second logical values; and a fraud detection processing unit that executes post-fraud-detection processing, when the first and second logical values do not coincide.
    Type: Application
    Filed: June 20, 2018
    Publication date: November 1, 2018
    Inventor: Makoto FUJIWARA
  • Patent number: 10032935
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: July 24, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Masaaki Higuchi, Masao Shingu, Tatsuya Kato, Takeshi Murata, Makoto Fujiwara, Masaki Kondo, Muneyuki Tsuda, Takashi Kurusu
  • Patent number: 10020364
    Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 10, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamasaki, Makoto Fujiwara, Shinji Mori
  • Patent number: 9804345
    Abstract: An optical module-member is provided, including: a layer-shaped optical waveguide; a light-emitting unit substrate including an insulating substrate, light-emitting element-mounting portions where light-emitting elements are configured to be mounted so as to be optically connected to the optical waveguide, and driving element-mounting portions which are electrically connected to the light-emitting element-mounting portions where driving elements for driving the light-emitting elements are configured to be mounted; and a light-receiving unit substrate which is separated from the light-emitting unit substrate, the light-receiving unit substrate including: an insulating substrate, light-receiving element-mounting portions where light-receiving elements are configured to be mounted so as to be optically connected to the optical waveguide, and signal amplification element-mounting portions which are electrically connected to the light-receiving element-mounting portions and where signal amplification elements for
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: October 31, 2017
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventors: Makoto Fujiwara, Shinya Arai
  • Publication number: 20170271527
    Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 21, 2017
    Inventors: Masaaki HIGUCHI, Masao SHINGU, Tatsuya KATO, Takeshi MURATA, Makoto FUJIWARA, Masaki KONDO, Muneyuki TSUDA, Takashi KURUSU
  • Patent number: 9754961
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: September 5, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroyuki Yamasaki, Makoto Fujiwara, Daisuke Nishida
  • Publication number: 20170141123
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of electrode layers; a first semiconductor film including a first portion and a second portion; a first insulating film having a lower surface; and a second semiconductor film having a lower surface. The first portion is provided as one body inside the stacked body. The first portion has a first crystal structure different from a crystal structure of the substrate. The second portion is provided between the first portion and the substrate. The second portion contacts the substrate and has a second crystal structure different from the first crystal structure.
    Type: Application
    Filed: February 29, 2016
    Publication date: May 18, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yosuke MITSUNO, Hiroshi Kanno, Makoto Fujiwara
  • Publication number: 20170077125
    Abstract: According to one embodiment, a semiconductor memory device includes a substrate; a stacked body including a plurality of insulating layers and including a first insulating layer and a plurality of conductive layers including a first conductive layer; a first semiconductor film extending in a stacking direction of the stacked body; a second semiconductor film, the second semiconductor film having a maximum thickness thicker than a maximum thickness of the first semiconductor film in a first direction crossing the stacking direction; and a first insulating film. The second semiconductor film has an upper face, and a height of the upper face is lower than a height of the first conductive layer. The first insulating film has a lower end portion, and a height of the lower end portion of the first insulating film is lower than the height of the upper face of the second semiconductor film.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 16, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki YAMASAKI, Makoto FUJIWARA, Daisuke NISHIDA
  • Publication number: 20170062451
    Abstract: A semiconductor memory device includes first and second electrode films, an interlayer insulating film, a semiconductor pillar, and a first insulating film. The first electrode film extends in a first direction. The second electrode film is provided separately from the first electrode film in a second direction and extends in the first direction. The interlayer insulating film is provided between the first and the second electrode films. The first insulating film includes first and second insulating regions. A concentration of nitrogen in the first position of the second insulating region is higher than a concentration of nitrogen in the second position between the first position and the semiconductor pillar. A concentration of nitrogen in the first insulating region is lower than the concentration of the nitrogen in the first position.
    Type: Application
    Filed: February 17, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masao SHINGU, Katsuyuki SEKINE, Hirokazu ISHIGAKI, Makoto FUJIWARA
  • Patent number: 9566847
    Abstract: A rear opening is provided in the rear part of a vehicle, and a tailgate opens and closes the rear opening. A spoiler is provided at the upper end of the tailgate. Deflectors are provided below the spoiler. The deflectors extend downward along the outer surface of the tail gate from the lower surface of the spoiler and are disposed at positions offset by a predetermined distance from the opposite ends in the vehicle width direction of the spoiler toward a central portion in the vehicle width direction of the spoiler.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: February 14, 2017
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Makoto Fujiwara, Kenichi Hori, Eiji Kimura, Kousuke Katsumata, Yuta Endo
  • Publication number: 20160282571
    Abstract: An optical module-member is provided, including: a layer-shaped optical waveguide; a light-emitting unit substrate including an insulating substrate, light-emitting element-mounting portions where light-emitting elements are configured to be mounted so as to be optically connected to the optical waveguide, and driving element-mounting portions which are electrically connected to the light-emitting element-mounting portions where driving elements for driving the light-emitting elements are configured to be mounted; and a light-receiving unit substrate which is separated from the light-emitting unit substrate, the light-receiving unit substrate including: an insulating substrate, light-receiving element-mounting portions where light-receiving elements are configured to be mounted so as to be optically connected to the optical waveguide, and signal amplification element-mounting portions which are electrically connected to the light-receiving element-mounting portions and where signal amplification elements for
    Type: Application
    Filed: July 1, 2014
    Publication date: September 29, 2016
    Applicant: SUMITOMO BAKELITE CO., LTD.
    Inventors: Makoto FUJIWARA, Shinya ARAI
  • Publication number: 20160272052
    Abstract: A rear opening is provided in the rear part of a vehicle, and a tailgate opens and closes the rear opening. A spoiler is provided at the upper end of the tailgate. Deflectors are provided below the spoiler. The deflectors extend downward along the outer surface of the tail gate from the lower surface of the spoiler and are disposed at positions offset by a predetermined distance from the opposite ends in the vehicle width direction of the spoiler toward a central portion in the vehicle width direction of the spoiler.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 22, 2016
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Makoto Fujiwara, Kenichi Hori, Eiji Kimura, Kousuke Katsumata, Yuta Endo
  • Publication number: 20160268379
    Abstract: One embodiment includes: forming a laminated body by alternately laminating a conducting layer and an interlayer insulating layer on a substrate; forming a memory hole passing through the laminated body; forming a memory gate insulating layer including a charge storage layer on an inner wall of the memory hole; forming a first semiconductor layer on the memory gate insulating layer; forming a cover film on the first semiconductor layer; removing the memory gate insulating layer, the first semiconductor layer, and the cover film on a bottom surface of the memory hole, to expose the substrate; forming an epitaxial layer on the exposed substrate; removing the cover film; and forming the second semiconductor layer along the first semiconductor layer, to electrically couple: the substrate to the first semiconductor layer; and the substrate to the second semiconductor layer, via the epitaxial layer.
    Type: Application
    Filed: September 10, 2015
    Publication date: September 15, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki YAMASAKI, Makoto FUJIWARA, Shinji MORI
  • Patent number: RE46997
    Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: August 14, 2018
    Assignee: Sony Corporation
    Inventors: Masahiro Igarashi, Tetsuo Motomura, Ryuji Kaneko, Makoto Fujiwara, Yoshinori Tanaka, Hiromi Ogata