Abstract: In the case where a target device stores: m keys {Ka1, . . . , Kam} (m is a natural number) in a manner that the Kai (i is a natural number satisfying 1?i?m) is encrypted with the Ka (i?1); and n keys {Kb1, . . . , Kbn} (n is a natural number) in a manner that the Kbj (j is a natural number satisfying 1?j?n) is encrypted with the Kb (j?1), a confidential information processing unit is caused to perform a processing of re-encrypting the encrypted key Enc (Kai, Ka (i?1)), which has been encrypted with the Ka (i?1), by using the Kb (j?1) and outputting as an encrypted key Enc (Kai, Kb (j?1)).

Abstract: Embodiments in accordance with the present invention provide waveguide structures and methods of forming such structures where core and laterally adjacent cladding regions are defined. Some embodiments of the present invention provide waveguide structures where core regions are collectively surrounded by laterally adjacent cladding regions and cladding layers and methods of forming such structures.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A lens barrel comprising bayonet type mount projections to detachably attach to a lens-fitting unit of a camera body having a photographic region, wherein mount projections are formed to avoid cross-section of light path area where object light is introduced in the camera body.

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract: A card host LSI includes M card host I/Fs for N-bit card modules, and M card bus terminals. A bridge circuit sets coupling relationship of signal lines so that a card host I/F corresponding to a card bus coupled to an (M×N)-bit card module and the other card host I/F(s) operate in conjunction with each other to control the card module, when an enable signal indicates the (M×N)-bit mode.

Abstract: A bearing roller chain which is sealed by a seal mechanism which prevents entry of foreign substances from the outside and leakage of lubricating oil leakage from the inside to the outside, resulting in an improvement in wear resistance of the bearing roller and avoidance both of rotation failure of the roller and of increased traveling resistance of the chain. A seal mechanism is provided between an inner link plate of a bearing roller chain and a bearing roller assembly carried by the link plate. The bearing roller assembly is formed by a plurality of anti-friction rollers between a hollow roller and a bush. The seal mechanism comprises an inner annular oil seal member, a spacer and a disk-shaped seal member having a flange extended toward an outer side surface of the hollow roller loosely into an outer circumferential concave groove on an end surface of the hollow roller. The disk-shaped seal member slidably comes into close contact with the inner link plate and the spacer, respectively.

Abstract: Multi-gate metal oxide silicon transistors and methods of making multi-gate metal oxide silicon transistors are provided. The multi-gate metal oxide silicon transistor contains a bulk silicon substrate containing one or more convex portions between shallow trench regions; one or more dielectric portions over the convex portions; one or more silicon fins over the dielectric portions; a shallow trench isolation layer in the shallow trench isolation regions; and a gate electrode. The upper surface of the shallow trench isolation layer can be located below the upper surface of the convex portion, or the upper surface of the shallow trench isolation layer can be located between the lower surface and the upper surface of first dielectric layer. The multi-gate metal oxide silicon transistor can contain second spacers adjacent to side surfaces of the convex portions in a source/drain region.

Abstract: A bus arbitration apparatus according to this invention appropriately arbitrates bus rights of use between a plurality of masters and a plurality of slaves so as to efficiently perform requested data transfer. An arbiter A 5 receives data transfer requests with respect to a slave A 3 generated by masters A 1 and B 2. The arbiter A 5 cooperates with an arbiter B 4, and arbitrates a contention of the data transfer requests with respect to the slave A 3 generated by the masters A 1 and B 2.

Abstract: A security information implementation system includes a storage section 120a for storing first encrypted security information EDK (MK) provided by encrypting final security information DK according to internal security information MK and second encrypted security information EMK (CK) provided by encrypting the internal security information MK according to conversion security information CK and an LSI 120b including a seed generation section 131 for storing a first constant value containing address information on which a conversion seed is generated based and a second constant value and a third constant value on which a test conversion seed is generated based and outputting the first constant value and the second constant value or the third constant value as the conversion seed or the test conversion seed in response to a test signal and a mode setup value; a one-way function circuit 32 for converting the conversion seed or the test conversion seed output from the seed generation section 131 according to the f

Abstract: A semiconductor integrated circuit includes: a first voltage line on which a specific one of a power-supply voltage and a reference voltage appears; a second voltage line; a plurality of circuit cells each receiving power generated as a difference between a voltage appearing on the second voltage line and the other one of the power-supply voltage and the reference voltage; a plurality of switch transistors connected in parallel between the first and second voltage lines to serve as switch transistors including switch transistors each having different conducting-state resistances; and a switch conduction control section for controlling a transition of each of the switch transistors from a non-conducting state to a conducting state by turning on the switch transistors at separate points of time.

Abstract: A semiconductor device according to an embodiment includes: a fin type MOSFET having a first gate electrode, and a first gate insulating film for generating Fermi level pinning in the first gate electrode; and a planar type MOSFET having a second gate electrode, and a second gate insulating film for generating no Fermi level pinning in the second gate electrode, or generating Fermi level pinning weaker than that generated in the first gate electrode in the second gate electrode.

Abstract: A check computation circuit executes a computation corresponding to a computation for generating confidential CRC data, with respect to confidential data read from a non-volatile device. A comparison circuit compares the result of the computation in the check computation circuit with confidential CRC data read from the non-volatile device. When the result of the comparison indicates a mismatch, i.e., an error is detected, an encryption circuit encrypts the confidential data and the confidential CRC data using a secret key registered in a secret key register, and outputs the encrypted confidential data and confidential CRC data to the outside of a semiconductor integrated circuit.

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract: In a set device having a card host LSI, high-speed data transmission to a removable card or the like is realized without hindering a reduction in size and weight. The card host LSI and the removable card are connected to a card bus complying with predetermined card bus specifications. A microcomputer module and the card host LSI are connected also by a card bus complying with the predetermined card bus specifications.

Abstract: A system including a secure LSI 1 establishes a communication path to/from a server 3 (UD1), and receives a common key-encrypted program generated by encryption with a common key and transmitted from the server 3 (UD6 and UD7). The received common key-encrypted program is decrypted to generate a raw program, and the raw program is re-encrypted with an inherent key to newly generate an inherent key-encrypted program, which is stored in an external memory.

Abstract: In order to maintain the confidentiality of information at a high level even in cases where a confidential information processor in which multiple types of decryption sequences are applicable is used, decryption is performed according to the value of content decryption information 304. If the value of the content decryption information 304 is “0”, an encrypted content key 309 is decrypted with a selected authentication intermediate key 312 and encrypted contents 310 are decrypted with a content key 305. On the other hand, if the value of the content decryption information 304 is other than “0”, the selected authentication intermediate key 312 is converted by performing an arithmetic operation using that value, thereby generating a conversion intermediate key 315. An encrypted domain key 316 is decrypted with the conversion intermediate key 315, the encrypted content key 309 is decrypted with a domain key 306, and then the encrypted contents 310 are decrypted with a content key 305.

Abstract: A secure LSI device 1 includes an encryption section 2 for encrypting a program, and an external I/F 50 for inputting/outputting a program or data from/to an external memory 100. In the encryption section 2, the operation of a private key arithmetic processing section 20 is prohibited with respect to a sequence whose execution is determined by a key-generation/update sequencer 30 to be impermissible. In the external I/F 50, a program processing section 51 and a data processing section 55 are structured independently from each other.

Abstract: Embodiments in accordance with the present invention provide waveguide structures and methods of forming such structures where core and laterally adjacent cladding regions are defined. Some embodiments of the present invention provide waveguide structures where core regions are collectively surrounded by laterally adjacent cladding regions and cladding layers and methods of forming such structures.

Abstract: A control device performs reading of data from a recording medium or writing of data into the recording medium. The control device includes a plurality of processing sections for performing at least any one of encrypting and decrypting processes, a plurality of interface sections serving as an interface to the recording medium respectively, and a controlling section for allocating one of the plurality of processing sections and one of the plurality of interface sections to each type of contents read from the recording medium or each type of contents written into the recording medium respectively. The control device encrypts or decrypts a plurality of contents in parallel.