Abstract: A data management system that enables appropriate management of data in offices is provided. A data management system including one or more server devices provided in each of a plurality of offices, in which: when receiving a request for data of another office from a client terminal, a setting unit sets information indicating acquisition of data of the other office in setting information; and an acquisition unit acquires the data of the other office from the server device in the other office according to the setting information in which a change is detected by a monitoring unit.

Abstract: An entertainment apparatus is configured to enable a program for an older version of the apparatus to be executed. In a normal mode, a main processing unit (MPU) operates as a main CPU, a graphics processor (GP) operates as a graphics processor, and an input/output subprocessor (IOP) operates as a subprocessor for input and output. In a compatible mode in which a program for an older version of the apparatus is executed, the IOP capable of executing the program for the older version of the apparatus operates as a main CPU, and the MPU and GP emulate a graphics processor for the older version of the apparatus.

Abstract: An information processing apparatus has a DRAM for storing at least predetermined data, a system bus to which the DRAM is connected, a CPU for controlling the DRAM, and a CPU bus to which the CPU is connected. The information processing apparatus also has an SRAM connected to the system bus and the CPU bus, for storing data transferred from the DRAM, an address counter for generating an address of the SRAM based on an initial value, and a DMA controller for controlling data transfer between the DRAM and the SRAM using the address generated by the address counter. At a certain time, the DMA controller outputs an address D2 next to an initial address in the DRAM via the system bus to the DRAM, reads data B from the address D2, and outputs the data B via the system bus to the SRAM. At the same time, the address counter increments a stored address S1 into an address S2, and outputs the address S2 to the SRAM, which stores the data B at the address S2.

Abstract: A video entertainment system includes a media processor for processing information. The media processor has a system bus with an external device connected thereto, a bus arbiter for providing the right to use the system bus to the external device in response to a request from the external device, a DRAM for storing a program supplied from the external device via the system bus, and digital signal processors for executing a predetermined process based on the program supplied from the DRAM. A CPU manages the process executed by the digital signal processors based on the program supplied from the DRAM.

Abstract: There is provided an image generation apparatus which requires a small amount of data for a draw command and a small capacity for a mixing ratio memory and which is capable of performing full transparent and full opaque processes utilizing a semitransparent process at high speed.

Abstract: Logical addresses start from different base addresses for respective numbers of bits of data making up words. One physical address in a main memory corresponds to a plurality of logical addresses, and an address converter has an association table of physical and logical addresses. The address converter decides which base address an entered logical address belongs to for thereby determining the number of bits of data of one word, and determines a physical address so as to be able to read words corresponding to the number of bits from the main memory. Words made up of different numbers of bits can quickly be converted from logical addresses into physical addresses.

Abstract: There is disclosed an entertainment apparatus on which a program for an older version of the apparatus can be executed. In a normal mode, an MPU(100) operates as a main CPU:and a GP(110) operates as a graphics processor, and an IOP(120) operates as a subprocessor for input and output. In a compatible mode in which a program for an older version of the apparatus is executed, the IOP(120) capable of executing the program for the older version of the apparatus operates as a main CPU, and the MPU(100) and GP(110) emulate a graphics processor for the older version of the apparatus.

Abstract: An image processing apparatus includes two devices which reproduce data on a disk. The devices operate independently of one another, thereby enabling image data from the disks to be processed rapidly.

Abstract: A device to perform tone generation while efficiently using a broad bit width bus and essentially eliminating the delay from the request for tone expression until its expression. An arithmetic processing device that generates tones reads the data all at once from a memory in which tone data is stored. This is set so that the delay time from when there is a request for tone generation until the tone is actually generated and expressed is negligible.

Abstract: A data format is provided capable of assigning a desired color lookup table (CLUT) to a texture pattern of each polygon drawn on a two-dimensional display screen. Assuming that TPF represents a pixel depth of the texture pattern, when TPF is 00, 01, and 10, the format (CLUT) is applied of a 4-bit mode, an 8-bit mode, and 16-bit mode respectively, whereby its related command is decreased in word length and thus requires less storage in a source video memory.

Abstract: An image processing system for producing an image from three-dimensional image data. The system uses a command generator to generate one or more plotting commands for producing the image, and features a coordinate calculator for transforming the three-dimensional data into two-dimensional data. The coordinate calculator operates as a coprocessor of the command generator, and as such does not require use of the system bus to perform its functions.

Abstract: Sound source data is constituted by a 14-byte sound data area SA consisting of 28 samples of 4-bit adaptive differential PCM data and a sound parameter area PA consisting of loop information LP, filter information FL and a shift amount RA.In encoding the sound source data, a CD-ROM XA encoder may be employed.4-bit ADPCM data is decoded by a BRR decoder 53, pitch-converted by a pitch conversion unit 54, and then processed with envelope transform by an envelope generator 58. After that, sound outputs of left and right channels outputted with the sound volume adjusted by volumes 60L, 60R, and 16-bit PCM data with the sound volume adjusted by a mixing volume 65, are added by an adder 62. Further, the sound data from the mixing volume 65, or an addition output produced by adding the sound data from the mixing volume 65 with the sound data from the volumes 60L, 60R, is reverberated by a reverberation processor 68.

Abstract: Image processing method and apparatus for producing an image from image data provides an image memory including a drawing area to store image data of an object to be drawn and a texture area to store texture data to decorate the object, a supply circuit for supplying image data to the image memory, a selector for selectively supplying the image data from the supply circuit to the drawing area and the texture area, an image synthesizing circuit for synthesizing an image from the image data stored in the image memory and an output circuit for converting an output signal from the image synthesizing circuit to a video signal for outputting the video signal. The method provides the steps of storing image data of an object to be drawn in a drawing area of an image memory, storing moving image data in a texture area of the image memory, and mapping a texture of the moving image stored in the texture area onto the surface of the object stored in the drawing area.

Abstract: A method and apparatus for generating images wherein access to a main memory is minimized during a translation of an image of a 3D object or the like on a display screen to increase the speed of the translation process. A string of draw commands for drawing an image is preceded by an offset draw command which indicates offset values for the coordinates of the vertices of the image, and the image is translated on the display screen in accordance with the offset draw command. A header portion of each of the offset draw command and the draw commands that constitute the draw command string includes data indicating the address on the main memory of the next draw command to be executed.

Abstract: In an apparatus provided with a frame memory for sequentially reading image data written in the frame memory for image display data, an image processing apparatus includes: a recognizing section for recognizing whether the image data written in the frame memory are image data in which each pixel is written with a first bit number or image data in which each pixel is written with a second bit number that is different from the first bit number; a first image data reading section for reading the image data from the frame memory, regarding each pixel as being expressed by the first bit number; a second image data reading section for reading the image data from the frame memory, regarding each pixel as being expressed by the second bit number; and a switching section for switching the first image data reading section and the second image data reading section on the basis of the recognition information from the recognizing section.

Abstract: Methods and apparatus for generating image data are provided. A memory and a data processor are coupled with a system bus. In certain embodiments a data expanding apparatus is also coupled to the system bus and compressed data are transferred to the data expanding apparatus via the system bus and decompressed data are transferred therefrom to the memory without passing the compressed data through the data processor. Also in certain embodiments, an image data generation command string is transferred from the memory to an image data generation device via the system bus without passing the image data generation command string through the data processor.

Abstract: An apparatus for video signal processing satisfactorily synthesizes images by using field memories and includes control circuit for controlling an operation for making an image, first and second field memories in which image data is written under the control of the control circuit, and output circuit for outputting image data alternately read out from the first and second field memories at a field period as a video signal to be displayed in an interlace fashion, wherein a vertical direction coordinate of coordinate data written in the second memory is shifted from a vertical coordinate written in the first field memory by half of a horizontal line.

Abstract: Methods and apparatus are provided for producing image data representing a picture from first two-dimensional image data producing instructions for producing two-dimensional image data and three-dimensional image data producing instructions for producing three-dimensional image data. Two-dimensional image data producing instructions are derived from the three-dimensional image data producing instructions. Display data producing priorities are assigned to the various two-dimensional image data producing instructions. Image data are produced by executing the various two-dimensional image data producing instructions in an order corresponding to the assigned image data producing priorities. The image data include a plurality of pixels each having a corresponding picture location and the pixels are stored in a memory such that first pixels produced after second pixels having the same corresponding picture locations overwrite the second pixels.

Abstract: An electronic sound source comprises an adder which calculates a sum of volume data and differential volume data in response to each clock signal supplied at equal intervals of time and transfers it to a limiter and a volume register. The sum volume data is then limited to a predetermined value by the limiter and passed across a volume register to a volume controller where it is multiplied by an output of a mute processor.

Abstract: An apparatus for generating the interrupt information includes an addressing device for generating the specified address information for specifying the desired information stored in a memory device, a readout address generating device for generating the readout address information of the desired information stored in the memory device, and a comparator device for comparing the specified address information from the addressing device and the readout address information from the readout address generating device and for generating the interrupt information in case of coincidence of the specified address information and the readout address information and supplying the interrupt information to a central processing unit.