Patents by Inventor Makoto Furuno

Makoto Furuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10529556
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: January 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Makoto Furuno
  • Publication number: 20170301538
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Application
    Filed: June 29, 2017
    Publication date: October 19, 2017
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Makoto FURUNO
  • Patent number: 9698008
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 4, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Makoto Furuno
  • Publication number: 20150214043
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventors: Shunpei YAMAZAKI, Junichiro SAKATA, Makoto FURUNO
  • Patent number: 9044793
    Abstract: A method for cleaning a hot-wall type film formation apparatus having a batch processing system with industrially high mass productivity is provided. In the method, a carbon film deposited on an inner wall or the like of a reaction chamber of the apparatus is removed efficiently in a short time. To remove the carbon film deposited on the inner wall of the reaction chamber by a thermal CVD method, the reaction chamber is heated at a temperature higher than or equal to 700° C. and lower than or equal to 800° C., and oxygen is introduced into the reaction chamber.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Toriumi, Makoto Furuno
  • Patent number: 9006046
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Makoto Furuno
  • Patent number: 8987068
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Patent number: 8846530
    Abstract: To provide a method for manufacturing a power storage device which enables improvement in performance of the power storage device, such as an increase in discharge capacity. To provide a method for forming a semiconductor region which is used for a power storage device or the like so as to improve performance. A method for forming a crystalline semiconductor region includes the steps of: forming, over a conductive layer, a crystalline semiconductor region that includes a plurality of whiskers including a crystalline semiconductor by an LPCVD method; and performing heat treatment on the crystalline semiconductor region after supply of a source gas containing a deposition gas including silicon is stopped. A method for manufacturing a power storage device includes the step of using the crystalline semiconductor region as an active material layer of the power storage device.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: September 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Makoto Furuno, Takashi Shimazu
  • Patent number: 8729620
    Abstract: It is an object to provide a nonvolatile semiconductor memory device having excellent writing property and charge-retention property. A semiconductor layer including a channel forming region between a pair of impurity regions which are formed to be apart from each other is provided. In an upper layer portion thereof, a first insulating layer, a floating gate, a second insulating layer, and a control gate are provided. The floating gate has at least a two-layer structure, and a first layer in contact with the first insulating layer preferably has a band gap smaller than that of the semiconductor layer. Furthermore, by setting an energy level at the bottom of the conduction band of the floating gate lower than that of the channel forming region of the semiconductor layer, injectability of carriers and a charge-retention property can be improved.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yoshinobu Asami, Tamae Takano, Makoto Furuno
  • Publication number: 20140080238
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Application
    Filed: November 15, 2013
    Publication date: March 20, 2014
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Shinji MAEKAWA, Makoto FURUNO, Osamu NAKAMURA, Keitaro IMAI
  • Patent number: 8643182
    Abstract: Provided are a semiconductor film including silicon microstructures formed at high density, and a manufacturing method thereof. Further, provided are a semiconductor film including silicon microstructures whose density is controlled, and a manufacturing method thereof. Furthermore, a power storage device with improved charge-discharge capacity is provided. A manufacturing method in which a semiconductor film with a silicon layer including silicon structures is formed over a substrate with a metal surface is used. The thickness of a silicide layer formed by reaction between the metal and the silicon is controlled, so that the grain sizes of silicide grains formed at an interface between the silicide layer and the silicon layer are controlled and the shapes of the silicon structures are controlled. Such a semiconductor film can be applied to an electrode of a power storage device.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: February 4, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Takayuki Inoue, Makoto Furuno
  • Patent number: 8629442
    Abstract: At least one or more of a conductive layer which forms a wiring or an electrode and a pattern necessary for manufacturing a display panel such as a mask for forming a predetermined pattern is formed by a method capable of selectively forming a pattern to manufacture a liquid crystal display device. A droplet discharge method capable of forming a predetermined pattern by selectively discharging a droplet of a composition in accordance with a particular object is used as a method capable of selectively forming a pattern in forming a conductive layer, an insulating layer, or the like.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: January 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Keitaro Imai
  • Publication number: 20130337607
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Application
    Filed: August 26, 2013
    Publication date: December 19, 2013
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Makoto Furuno
  • Patent number: 8592908
    Abstract: To provide a semiconductor substrate including a crystalline semiconductor layer which is suitable for practical use, even if a material different from that of the semiconductor layer is used for a supporting substrate, and a semiconductor device using the semiconductor substrate. The semiconductor substrate includes a bonding layer which forms a bonding plane, a barrier layer formed of an insulating material containing nitrogen, a relief layer which is formed of an insulating material that includes nitrogen at less than 20 at. % and hydrogen at 1 at. % to 20 at. %, and an insulating layer containing a halogen, between a supporting substrate and a single-crystal semiconductor layer. The semiconductor device includes the above-described structure at least partially, and a gate insulating layer formed by a microwave plasma CVD method using SiH4 and N2O as source gases is in contact with the single-crystal semiconductor layer.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: November 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuhiro Ichijo, Makoto Furuno, Takashi Ohtsuki, Kenichi Okazaki, Tetsuhiro Tanaka, Seiji Yasumoto
  • Publication number: 20130270679
    Abstract: Provided are a semiconductor film including silicon microstructures formed at high density, and a manufacturing method thereof. Further, provided are a semiconductor film including silicon microstructures whose density is controlled, and a manufacturing method thereof. Furthermore, a power storage device with improved charge-discharge capacity is provided. A manufacturing method in which a semiconductor film with a silicon layer including silicon structures is formed over a substrate with a metal surface is used. The thickness of a silicide layer formed by reaction between the metal and the silicon is controlled, so that the grain sizes of silicide grains formed at an interface between the silicide layer and the silicon layer are controlled and the shapes of the silicon structures are controlled. Such a semiconductor film can be applied to an electrode of a power storage device.
    Type: Application
    Filed: June 3, 2013
    Publication date: October 17, 2013
    Inventors: Tomokazu YOKOI, Takayuki INOUE, Makoto FURUNO
  • Patent number: 8518761
    Abstract: An object is to provide a deposition method in which a gallium oxide film is formed by a DC sputtering method. Another object is to provide a method for manufacturing a semiconductor device using a gallium oxide film as an insulating layer such as a gate insulating layer of a transistor. An insulating film is formed by a DC sputtering method or a pulsed DC sputtering method, using an oxide target including gallium oxide (also referred to as GaOX). The oxide target includes GaOX, and X is less than 1.5, preferably more than or equal to 0.01 and less than or equal to 0.5, further preferably more than or equal to 0.1 and less than or equal to 0.2. The oxide target has conductivity, and sputtering is performed in an oxygen gas atmosphere or a mixed atmosphere of an oxygen gas and a rare gas such as argon.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Makoto Furuno
  • Patent number: 8455044
    Abstract: Provided are a semiconductor film including silicon microstructures formed at high density, and a manufacturing method thereof. Further, provided are a semiconductor film including silicon microstructures whose density is controlled, and a manufacturing method thereof. Furthermore, a power storage device with improved charge-discharge capacity is provided. A manufacturing method in which a semiconductor film with a silicon layer including silicon structures is formed over a substrate with a metal surface is used. The thickness of a silicide layer formed by reaction between the metal and the silicon is controlled, so that the grain sizes of silicide grains formed at an interface between the silicide layer and the silicon layer are controlled and the shapes of the silicon structures are controlled. Such a semiconductor film can be applied to an electrode of a power storage device.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: June 4, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomokazu Yokoi, Takayuki Inoue, Makoto Furuno
  • Patent number: 8395158
    Abstract: The present invention relates to a semiconductor device including a thin film transistor comprising a microcrystalline semiconductor which forms a channel formation region and includes an acceptor impurity element, and to a manufacturing method thereof. A gate electrode, a gate insulating film formed over the gate electrode, a first semiconductor layer which is formed over the gate insulating film and is formed of a microcrystalline semiconductor, a second semiconductor layer which is formed over the first semiconductor layer and includes an amorphous semiconductor, and a source region and a drain region which are formed over the second semiconductor layer are provided in the thin film transistor. A channel is formed in the first semiconductor layer when the thin film transistor is placed in an on state.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 12, 2013
    Assignee: Semiconductor Energy Labortory Co., Ltd.
    Inventors: Shunpei Yamazaki, Makoto Furuno
  • Publication number: 20130023108
    Abstract: An insulating layer is formed on a surface of a semiconductor wafer which is to be a bond substrate and an embrittlement region is formed in the semiconductor wafer by irradiation with accelerated ions. Then, a base substrate and the semiconductor wafer are attached to each other. After that, the semiconductor wafer is divided at the embrittlement region by performing heat treatment and an SOI substrate including a semiconductor layer over the base substrate with the insulating layer interposed therebetween is formed. Before the SOI substrate is formed, heat treatment is performed on the semiconductor wafer at a temperature of higher than or equal to 1100° C. under a non-oxidizing atmosphere in which the concentration of impurities is reduced. In this manner, the planarity of the film formed on the semiconductor wafer when heat treatment is performed can be improved.
    Type: Application
    Filed: July 18, 2012
    Publication date: January 24, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kazuya HANAOKA, Yujiro SAKURADA, Hideki TSUYA, Makoto FURUNO, Miku FUJITA
  • Patent number: 8310474
    Abstract: When semi-amorphous TFTs are used for forming a signal line driver circuit and a pixel, a large amplitude is required for driving the pixel, and a large power supply voltage is thus needed. On the other hand, when a shift register is made up of transistors having a single conductivity, a bootstrap circuit is required, and a voltage over a power supply is applied to a specific element. Therefore, not both the driving amplitude and the reliability can be achieved with a single power supply. According to the invention, a level shifter having a single conductivity is provided to solve such a problem.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: November 13, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Keitaro Imai, Shinji Maekawa, Makoto Furuno, Osamu Nakamura, Shunpei Yamazaki