Abstract: To provide a technique capable of improving performance and reliability of a semiconductor device. An n?-type epitaxial layer (12) is formed on an n-type semiconductor substrate (11), and a p+-type body region (14), n+-type current spreading regions (16, 17), and a trench. TR are formed in the n?-type epitaxial layer (12). A bottom surface B1 of the trench TR is located in the p+-type body region (14), a side surface S1 of the trench TR is in contact with the n+-type current spreading region (17), and a side surface S2 of the trench TR is in contact with the n+-type current spreading region (16). Here, a ratio of silicon is higher than a ratio of carbon in an upper surface T1 of the n?-type epitaxial layer (12), and the bottom surface B1, the side surface S1, and the side surface 32 of the trench.

Abstract: In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.

Abstract: In a method for manufacturing a device fabrication wafer, an SiC epitaxial wafer that is an SiC wafer 40 having a monocrystalline SiC epitaxial layer formed thereon is subjected to a basal plane dislocation density reduction step of reducing the density of basal plane dislocations existing in the epitaxial layer of the SiC epitaxial wafer, to thereby manufacture the device fabrication wafer for use to fabricate a semiconductor device. In the basal plane dislocation density reduction step, the SiC epitaxial wafer is heated under Si vapor pressure for a predetermined time necessary to reduce the density of basal plane dislocations, without formation of a cap layer on the SiC epitaxial wafer, so that the density of basal plane dislocations is reduced with suppression of surface roughening.

Abstract: In a method for manufacturing an SiC wafer, a work-affected layer removal step of removing a work-affected layer generated in a surface and inside of an SiC wafer is performed, so that the SiC wafer from which the work-affected layer is at least partially removed is manufactured. In the work-affected layer removal step, the SiC wafer having undergone a polishing step is etched with an etching amount of 10 ?m or less by being heated under Si vapor pressure so that the work-affected layer is removed. In the polishing step, an oxidizer is used to produce a reaction product in the SiC wafer while abrasive grains are used to remove the reaction product. In the SiC wafer having undergone the polishing step, an internal stress caused by the work-affected layer is present at a location inner than the work-affected layer, and an internal stress of the SiC wafer is reduced by removing the work-affected layer in the work-affected layer removal step.

Abstract: An object is to provide a SiC wafer in which a detection rate of an optical sensor can improved and a SiC wafer manufacturing method. The method includes: a satin finishing process S141 of satin-finishing at least a back surface 22 of a SiC wafer 20; an etching process 21 of etching at least the back surface 22 of the SiC wafer 20 by heating under Si vapor pressure after the satin finishing process S141; and a mirror surface processing process S31 of mirror-processing a main surface 21 of the SiC wafer 20 after the etching process S21. Accordingly, it is possible to obtain a SiC wafer having the mirror-finished main surface 21 and the satin-finished back surface 22.

Abstract: In a method for manufacturing a reformed SiC wafer 41 (a surface treatment method for a SiC wafer) having its surface that is reformed by processing an untreated SiC wafer 40 before formation of an epitaxial layer 42, the method includes a surface reforming step as described below. That is, the untreated SiC wafer 40 includes BPDs as dislocations parallel to an inside of a (0001) face, and TEDs. Property of the surface of the untreated SiC wafer 40 is changed so as to have higher rate in which portions having BPDs on the surface of the untreated SiC wafer 40 propagate as TEDs at a time of forming the epitaxial layer 42.

Abstract: Provided is a method for manufacturing a thin SiC wafer by which a SiC wafer is thinned using a method without generating crack or the like, the method in which polishing after adjusting the thickness of the SiC wafer can be omitted. The method for manufacturing the thin SiC wafer 40 includes a thinning step. In the thinning step, the thickness of the SiC wafer 40 can be decreased to 100 ?m or less by performing the Si vapor pressure etching in which the surface of the SiC wafer 40 is etched by heating the SiC wafer 40 after cutting out of an ingot 4 under Si vapor pressure.

Abstract: To aim to reduce ripple current flowing through a capacitor in a power converter apparatus including a converter, the capacitor and an inverter. A current sensor 6 is connected between a capacitor 5 and an inverter circuit 7 for detecting current Iinv flowing from the capacitor 5 to the inverter circuit 7. A frequency detecting subunit 11 performs fast Fourier transform on a waveform of the current Iinv to detect a frequency of a frequency component having the largest amplitude. Also, the frequency detecting subunit 12 detects a zero-cross point of the frequency component having the largest amplitude. Then a carrier signal control subunit 13 performs control such that a frequency and a rise time of a PWM carrier signal for driving the converter circuit 4 match the frequency and the zero-cross point that have been detected by the frequency detecting subunit 11 and the phase detecting subunit 12.

Abstract: A synchronous motor drive system improves the design flexibility regarding torque characteristics as compared with conventionally available design flexibility. A synchronous motor has a rotor and a stator. Each of at least two adjacent stator teeth has a slit formed at the tip thereof. Each of a plurality of stator teeth has a main coil wound therearound in concentrated winding. Between each two adjacent teeth having a slit, a sub-coil is wound around in a manner of being accommodated in the respective slits. The drive device separately controls electric current supplied to the main coils and electric current supplied to the sub-coil.

Abstract: A power converter for effectively reducing switching noise is provided. The power converter comprises a capacitor 111; switching devices Q11a and Q11b connected to the capacitor 111 in parallel; and a controller 105 that controls each switching device individually to perform switching operations. Each of the switching devices Q11a and Q11b forms a closed circuit together with the capacitor 111. The controller 105 controls the switching devices Q11a and Q11b to perform switching operations of switching ON or OFF at different timings such that at least two closed circuits including the switching devices Q11a and Q11b mutually cancel ringing voltages occurring therein, each ringing voltage occurring due to the switching operations performed by a corresponding switching device and having a frequency defined by an inductance of a corresponding closed circuit and an output capacity of a switching device included in the corresponding closed circuit.

Abstract: A semiconductor element according to the present invention can perform both a transistor operation and a diode operation via its channel layer. If the potential Vgs of its gate electrode 165 with respect to that of its source electrode 150 is 0 volts, then a depletion layer with a thickness Dc, which has been depleted entirely in the thickness direction, is formed in at least a part of the channel layer 150 due to the presence of a pn junction between a portion of its body region 130 and the channel layer 150, and another depletion layer that has a thickness Db as measured from the junction surface of the pn junction is formed in that portion of the body region 130.

Abstract: An inverter comprising: a circuit including arms connected in parallel, each of the arms including a first switch and a second switch connected in series; and a gate drive circuit configured to control, by pulse-width modulation using synchronous rectification, each of the first switch and the second switch to switch to an on-state or an off-state, wherein each of the first switch and the second switch includes: a channel region that is conductive in both a forward direction and a reverse direction in the on-state, and that is not conductive in the forward direction in the off-state; and a diode region that is combined as one with the channel region, and that is conductive only in the reverse direction, the diode region being unipolar, and the gate drive circuit synchronizes a timing at which the gate drive circuit outputs a signal for causing the first switch to switch to the on-state with a timing at which the gate drive circuit outputs a signal for causing the second switch to switch to the off-state, and

Abstract: A small-sized load drive system which, even with three three-phase inverters, significantly reduces noise regardless of control duty ratio. The load drive system includes three-phase inverters, and first, second, and third control units. The inverters are connected to loads, respectively. The first control unit generates sawtooth wave voltage and controls the inverter according to the sawtooth wave voltage. The second control unit generates inverse sawtooth wave voltage and controls the inverter according to the inverse sawtooth wave voltage. The third control unit generates triangular wave voltage which has ramps respectively equal to the sawtooth/inverse sawtooth wave voltage and either has a same phase or is out of phase by half a period relative to the sawtooth/inverse sawtooth wave voltage, and also controls the inverter according to the triangular wave voltage.

Abstract: A synchronous electric motor includes rotor having a plurality of radially-oriented magnetic dipoles and a stator. Stator teeth group with a plurality of sets of stator teeth are arranged in the same position in terms of an electrical angle with another stator teeth group to provide rotational symmetry about an axis of the rotor. In each of the stator teeth groups a predetermined number of stator teeth are arranged at intervals different from intervals of the rotor magnetic dipoles. A main coil is wound about a predetermined number of stator teeth with a sub-coil further wound around one or more a teeth. Phase and magnitude of a resulting magnetic field is adjusted by the number of loops of the main coil and sub-coil. A given stator tooth can produce maximum torque despite any difference between an alignment of the stator tooth and an inter-polar interval of the stator.

Abstract: The present invention provides a synchronous motor drive system designed to realize reduced vibration and noise along with high output. The system includes: inverters 101, 102, and 103 for converting a direct current to a three-phase alternating current; a current application control unit 52 that controls operations of the three-phase inverters; and a synchronous motor 41 driven by three-phase alternating currents supplied from the three-phase inverters. The current application control unit 52 determines, for each three-phase inverter, a current phase angle and a current amount of a three-phase alternating current to output, and each inverter supplies a three-phase alternating current having the determined current phase angle and current amount to a different one of three-phase coil groups 200a to 200c.

Abstract: Provided is a synchronous motor including a rotor having magnetic poles distributed circumferentially along a rotation direction of the rotor at equal intervals, and a stator having stator teeth arranged circumferentially along the rotation direction of the rotor, each tooth wound with a stator coil by concentrated winding. Every M consecutive stator teeth belong to one of stator teeth groups arranged at equal intervals. The M consecutive stator teeth in each stator teeth group are arranged at intervals different from the intervals of the magnetic poles of the rotor. The stator coils wound around the M consecutive stator teeth are connected to separate terminals. A motor driver supplies currents of different phases to the stator coils via the respective terminals.

Abstract: A power converter for effectively reducing switching noise is provided. The power converter comprises a capacitor 111; switching devices Q11a and Q11b connected to the capacitor 111 in parallel; and a controller 105 that controls each switching device individually to perform switching operations. Each of the switching devices Q11a and Q11b forms a closed circuit together with the capacitor 111. The controller 105 controls the switching devices Q11a and Q11b to perform switching operations of switching ON or OFF at different timings such that at least two closed circuits including the switching devices Q11a and Q11b mutually cancel ringing voltages occurring therein, each ringing voltage occurring due to the switching operations performed by a corresponding switching device and having a frequency defined by an inductance of a corresponding closed circuit and an output capacity of a switching device included in the corresponding closed circuit.

Abstract: In a power conversion circuit operating with high frequency, an off-voltage control circuit 101u of a lower-arm gate drive circuit 24u controls the output voltage of a gate drive power supply 103u to change the output voltage to a voltage lower than a predetermined off voltage during a time period from termination of turn-off operation of a lower arm 22u until start of turn-on operation of an upper arm 21u, and thereafter return the output voltage to the predetermined off voltage immediately after termination of the turn-on operation of the upper arm 21u. With this control, short-circuiting through the upper and lower arms occurring due to a high voltage change dv/dt can be avoided, and the life of a switching element constituting the power conversion circuit improves, increasing the reliability of the power conversion circuit.

Abstract: An inverter comprising: a circuit including arms connected in parallel, each of the arms including a first switch and a second switch connected in series; and a gate drive circuit configured to control, by pulse-width modulation using synchronous rectification, each of the first switch and the second switch to switch to an on-state or an off-state, wherein each of the first switch and the second switch includes: a channel region that is conductive in both a forward direction and a reverse direction in the on-state, and that is not conductive in the forward direction in the off-state; and a diode region that is combined as one with the channel region, and that is conductive only in the reverse direction, the diode region being unipolar, and the gate drive circuit synchronizes a timing at which the gate drive circuit outputs a signal for causing the first switch to switch to the on-state with a timing at which the gate drive circuit outputs a signal for causing the second switch to switch to the off-state, and

Abstract: A converter utilizing synchronous rectification comprises a first switch, a second switch connected in series to the first switch, and a gate drive circuit controlling each switch to switch to on/off-state using pulse-width modulation. Each switch includes a channel region that is conductive in both forward and reverse directions in on-state and is not conductive in the forward direction in off-state, and a unipolar diode region conductive only in the reverse direction. The gate drive circuit synchronizes output timing for signal with which the first switch switches to on-state with output timing for signal with which the second switch switches to off-state, and synchronizes output timing for signal with which the first switch switches to off-state with output timing for signal with which the second switch switches to on-state.