Patents by Inventor Makoto Kitagawa

Makoto Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200020411
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Application
    Filed: March 13, 2018
    Publication date: January 16, 2020
    Inventors: HARUHIKO TERADA, MAKOTO KITAGAWA, YOSHIYUKI SHIBAHARA, YOTARO MORI
  • Publication number: 20190318782
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20190311767
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Publication number: 20190311688
    Abstract: During a drive period, luminance momentarily decreases when the value ?(A?B) is positive and momentarily increases when the value ?(A?B) is negative. When the luminance increases during a pause period in accordance with the balance in time constant between an alignment film and a liquid crystal material that are included in a pixel forming portion, primary and secondary parasitic capacitances are adjusted so as to set the value ?(A?B) to be negative.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 10, 2019
    Inventors: Makoto KITAGAWA, Hideki FUJIMOTO, Yusuke NISHIHARA
  • Patent number: 10438661
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 10395731
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Patent number: 10395730
    Abstract: A non-volatile memory device of the present disclosure includes: a plurality of bit lines; a plurality of word lines; a memory cell array having a plurality of memory cells each including a non-volatile storage element and being disposed at crossing sections of the bit lines and the word lines; a reference voltage generator circuit that generates a readout reference voltage serving as a reference for discrimination of data values stored on the memory cells; a readout circuit that reads the data values stored on the memory cells by detecting values of readout voltages from the memory cells relative to the readout reference voltage in a state where a predetermined current-limited readout current is applied to the bit lines; and an address compensation circuit that changes the readout reference voltage in accordance with a placement position of a memory cell to be read of the memory cells in the readout circuit.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 27, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yotaro Mori, Makoto Kitagawa
  • Patent number: 10304528
    Abstract: A memory device of one embodiment of the technology includes: a plurality of memory cells in a matrix arrangement; a plurality of row wirings each coupled to one end of each memory cell; a plurality of column wirings each coupled to another end of each memory cell, a first decoder circuit coupled to each of the row wirings of even-numbered rows; a second decoder circuit coupled to each of the row wirings of odd-numbered rows; a third decoder circuit coupled to each of the column wirings of even-numbered columns; and a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are constituted by independent circuits from one another.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 28, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Haruhiko Terada, Yotaro Mori, Makoto Kitagawa
  • Publication number: 20190143612
    Abstract: A fiber-reinforced resin hollow body includes an axial-direction fiber layer containing reinforcing fibers aligned parallel to an axial direction of the hollow body, and a non-axial-direction fiber layer provided on top of at least one of an internal and an external side of the axial-direction fiber layer, and containing reinforcing fibers oriented in a direction different from the alignment direction of the axial-direction fiber layer. The non-axial-direction fiber layer includes one or more peripheral-direction fiber layers containing reinforcing fibers aligned parallel to a peripheral direction of the hollow body, and one or more non-aligned fiber layers containing reinforcing fibers not aligned in a specific direction.
    Type: Application
    Filed: March 29, 2017
    Publication date: May 16, 2019
    Applicants: KURIMOTO, LTD., MAZDA MOTOR CORPORATION
    Inventors: Takeshi KITAGAWA, Masaya HAZAMA, Toshiki OKAUJI, Makoto TAKEDA, Jun WATANABE, Takashi TABAKOYA, Shin MATSUMURA, Yoshiyasu KAJIMOTO, Kazuhisa TO
  • Publication number: 20190139606
    Abstract: Memory systems and memory programming methods are described.
    Type: Application
    Filed: December 28, 2018
    Publication date: May 9, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Publication number: 20190135248
    Abstract: In this brake control device for a motorcycle, a deceleration threshold value calculation unit limits target wheel deceleration to a threshold value or less on the basis of a bank angle estimated by a bank angle calculation unit. Thus, the behavior of the vehicle body during turning of the motorcycle can be made more stable so as not to cause discomfort to a driver.
    Type: Application
    Filed: March 31, 2016
    Publication date: May 9, 2019
    Inventors: Chikashi IIZUKA, Makoto TODA, Hiroki KITAGAWA, Tetsuya HASEGAWA, Nobuyuki KODAIRA
  • Patent number: 10249366
    Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: April 2, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Makoto Kitagawa, Tomohito Tsushima, Wataru Otsuka, Takafumi Kunihiro
  • Publication number: 20190088224
    Abstract: Common electrodes are provided in a manner in which the common electrodes are divided into a common electrode for an odd column corresponding to a pixel electrode to which a positive video signal is applied in a certain frame period, and a common electrode for an even column corresponding to a pixel electrode to which a negative video signal is applied in the certain frame period. A common electrode driver is configured to be capable of separately applying a voltage to the common electrode for the odd column and the common electrode for the even column.
    Type: Application
    Filed: September 18, 2018
    Publication date: March 21, 2019
    Inventors: HIDEKI FUJIMOTO, MAKOTO KITAGAWA, YUSUKE NISHIHARA, YOSHITO HASHIMOTO
  • Publication number: 20190080759
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Application
    Filed: November 13, 2018
    Publication date: March 14, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20190066783
    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
    Type: Application
    Filed: October 31, 2018
    Publication date: February 28, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Kerry Tedrow
  • Publication number: 20190066784
    Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Yogesh Luthra
  • Patent number: 10176868
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Publication number: 20180366188
    Abstract: An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.
    Type: Application
    Filed: November 18, 2016
    Publication date: December 20, 2018
    Inventors: Makoto Kitagawa, Tomohito Tsushima, Wataru Otsuka, Takafumi Kunihiro
  • Patent number: 10147487
    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 4, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Kerry Tedrow
  • Patent number: 10121539
    Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: November 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Yogesh Luthra