Patents by Inventor Makoto Kitagawa

Makoto Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200394550
    Abstract: The quantum circuit learning device includes a signal input unit that provides a quantum circuit including plural quantum bits with an input signal, a signal acquisition unit that observes states of quantum bits that the quantum circuit includes and acquires an output signal based on the observed states, and an adjustment unit that adjusts a circuit parameter that defines a circuit configuration of the quantum circuit, using an output signal that the signal acquisition unit acquires and a cost function that is set based on a teacher signal corresponding to the output signal.
    Type: Application
    Filed: August 25, 2020
    Publication date: December 17, 2020
    Inventors: Keisuke Fujii, Makoto Negoro, Kosuke Mitarai, Masahiro Kitagawa
  • Publication number: 20200381049
    Abstract: Memory systems and memory programming methods are described.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 3, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Patent number: 10783961
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Publication number: 20200286953
    Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 10, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Makoto KITAGAWA, Yoshiyuki SHIBAHARA, Haruhiko TERADA, Yotaro MORI
  • Patent number: 10770143
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Patent number: 10748613
    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 18, 2020
    Assignee: MIcron Technology, Inc.
    Inventors: Makoto Kitagawa, Kerry Tedrow
  • Patent number: 10706925
    Abstract: A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an intersection of a first wiring and a second wiring, and includes a variable resistance element having a resistance state that is variable between a first resistance state and a second resistance state. The writing circuit varies the variable resistance element from the first resistance state to the second resistance state, and thereby performs writing of data on the memory cell. The current controller controls a current and thereby limits the current to a predetermined limit current value. The current is caused to flow through the first wiring or the second wiring by the writing circuit upon performing of the writing of the data.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yotaro Mori, Makoto Kitagawa
  • Publication number: 20200191735
    Abstract: The nuclear spin hyperpolarization method includes the steps of: irradiating a sample, prepared by doping solid benzoic acid derivative with a pentacene derivative, placed in a space where a static magnetic field is formed by a main magnetic field forming unit, with a laser beam from a laser source; following the light irradiation, irradiating the sample with a microwave from a microwave source while applying a sweeping magnetic field; and after repeating the application of sweeping magnetic field, light irradiation and microwave irradiation, dissolving the benzoic acid derivative in the sample. This enables generation of an aqueous solution containing benzoic acid derivative of which nuclear spins are hyperpolarized.
    Type: Application
    Filed: August 21, 2018
    Publication date: June 18, 2020
    Applicant: OSAKA UNIVERSITY
    Inventors: Makoto NEGORO, Masahiro KITAGAWA, Akinori KAGAWA
  • Patent number: 10650762
    Abstract: During a drive period, luminance momentarily decreases when the value ?(A?B) is positive and momentarily increases when the value ?(A?B) is negative. When the luminance increases during a pause period in accordance with the balance in time constant between an alignment film and a liquid crystal material that are included in a pixel forming portion, primary and secondary parasitic capacitances are adjusted so as to set the value ?(A?B) to be negative.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 12, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Kitagawa, Hideki Fujimoto, Yusuke Nishihara
  • Patent number: 10622067
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20200098425
    Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.
    Type: Application
    Filed: May 11, 2018
    Publication date: March 26, 2020
    Inventors: YOTARO MORI, MAKOTO KITAGAWA, JUN OKUNO, HARUHIKO TERADA
  • Patent number: 10564232
    Abstract: An object is to provide a method for enhancing a nuclear spin polarization. Triplet DNP where a pentacene derivative represented by the following formula (A) is used as a polarizing agent enables an effective enhancement in nuclear spin polarization to be achieved. In formula (A), each R independently represents a hydrogen atom (—H), a deuterium atom (-D), or a hydrocarbon group having 1 to 20 carbon atoms which optionally includes at least one atom selected from the group consisting of an oxygen atom, a sulfur atom and a silicon atom, provided that at least one R represents a hydrocarbon group having 1 to 20 carbon atoms which optionally includes at least one atom selected from the group consisting of an oxygen atom, a sulfur atom and a silicon atom.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: February 18, 2020
    Assignees: Riken, Osaka University
    Inventors: Kenichiro Tateishi, Tomohiro Uesaka, Makoto Negoro, Masahiro Kitagawa
  • Publication number: 20200020411
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Application
    Filed: March 13, 2018
    Publication date: January 16, 2020
    Inventors: HARUHIKO TERADA, MAKOTO KITAGAWA, YOSHIYUKI SHIBAHARA, YOTARO MORI
  • Publication number: 20190318782
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20190311767
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Publication number: 20190311688
    Abstract: During a drive period, luminance momentarily decreases when the value ?(A?B) is positive and momentarily increases when the value ?(A?B) is negative. When the luminance increases during a pause period in accordance with the balance in time constant between an alignment film and a liquid crystal material that are included in a pixel forming portion, primary and secondary parasitic capacitances are adjusted so as to set the value ?(A?B) to be negative.
    Type: Application
    Filed: April 3, 2019
    Publication date: October 10, 2019
    Inventors: Makoto KITAGAWA, Hideki FUJIMOTO, Yusuke NISHIHARA
  • Patent number: 10438661
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 10395730
    Abstract: A non-volatile memory device of the present disclosure includes: a plurality of bit lines; a plurality of word lines; a memory cell array having a plurality of memory cells each including a non-volatile storage element and being disposed at crossing sections of the bit lines and the word lines; a reference voltage generator circuit that generates a readout reference voltage serving as a reference for discrimination of data values stored on the memory cells; a readout circuit that reads the data values stored on the memory cells by detecting values of readout voltages from the memory cells relative to the readout reference voltage in a state where a predetermined current-limited readout current is applied to the bit lines; and an address compensation circuit that changes the readout reference voltage in accordance with a placement position of a memory cell to be read of the memory cells in the readout circuit.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 27, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yotaro Mori, Makoto Kitagawa
  • Patent number: 10395731
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Patent number: 10304528
    Abstract: A memory device of one embodiment of the technology includes: a plurality of memory cells in a matrix arrangement; a plurality of row wirings each coupled to one end of each memory cell; a plurality of column wirings each coupled to another end of each memory cell, a first decoder circuit coupled to each of the row wirings of even-numbered rows; a second decoder circuit coupled to each of the row wirings of odd-numbered rows; a third decoder circuit coupled to each of the column wirings of even-numbered columns; and a fourth decoder circuit coupled to each of the column wirings of odd-numbered columns. The first decoder circuit, the second decoder circuit, the third decoder circuit, and the fourth decoder circuit are constituted by independent circuits from one another.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: May 28, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Haruhiko Terada, Yotaro Mori, Makoto Kitagawa