Patents by Inventor Makoto Kitagawa

Makoto Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220295157
    Abstract: A content providing system is provided that includes a client terminal and a server, and provides content based on a use state of the client terminal. The client terminal includes a client control unit and a display unit. The server includes a client terminal management unit, a content recording unit, a content management unit, a content distribution control unit, and a distribution condition management unit. The client control unit secures a content frame based on a distribution condition notified from the distribution condition management unit, and transmits a distribution request of the content to the content distribution control unit. The content distribution control unit extracts and distributes the content from the content recording unit, and the client control unit displays the content distributed by the content distribution control unit on the display unit within the content frame.
    Type: Application
    Filed: February 4, 2019
    Publication date: September 15, 2022
    Inventors: Osamu KIKUCHI, Yasuaki TSUNEMI, Yukiko EINAGA, Tomonori KAIZAKI, Makoto KAWAMURA, Satoshi KOBAYASHI, Tomomi ABE, Xuan HAN, Ryuki KITAGAWA
  • Patent number: 11383459
    Abstract: A fiber-reinforced resin hollow body includes an axial-direction fiber layer containing reinforcing fibers aligned parallel to an axial direction of the hollow body, and a non-axial-direction fiber layer provided on top of at least one of an internal and an external side of the axial-direction fiber layer, and containing reinforcing fibers oriented in a direction different from the alignment direction of the axial-direction fiber layer. The non-axial-direction fiber layer includes one or more peripheral-direction fiber layers containing reinforcing fibers aligned parallel to a peripheral direction of the hollow body, and one or more non-aligned fiber layers containing reinforcing fibers not aligned in a specific direction.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: July 12, 2022
    Assignees: KURIMOTO, LTD., MAZDA MOTOR CORPORATION
    Inventors: Takeshi Kitagawa, Masaya Hazama, Toshiki Okauji, Makoto Takeda, Jun Watanabe, Takashi Tabakoya, Shin Matsumura, Yoshiyasu Kajimoto, Kazuhisa To
  • Publication number: 20220181338
    Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.
    Type: Application
    Filed: December 4, 2020
    Publication date: June 9, 2022
    Inventor: Makoto Kitagawa
  • Patent number: 11295812
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: April 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Patent number: 11024376
    Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yotaro Mori, Makoto Kitagawa, Jun Okuno, Haruhiko Terada
  • Patent number: 10991762
    Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 27, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Makoto Kitagawa, Yoshiyuki Shibahara, Haruhiko Terada, Yotaro Mori
  • Patent number: 10943668
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: March 9, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Haruhiko Terada, Makoto Kitagawa, Yoshiyuki Shibahara, Yotaro Mori
  • Patent number: 10937493
    Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 2, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Yogesh Luthra
  • Publication number: 20200381049
    Abstract: Memory systems and memory programming methods are described.
    Type: Application
    Filed: August 20, 2020
    Publication date: December 3, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Patent number: 10783961
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 22, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy
  • Publication number: 20200286953
    Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.
    Type: Application
    Filed: March 5, 2018
    Publication date: September 10, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Makoto KITAGAWA, Yoshiyuki SHIBAHARA, Haruhiko TERADA, Yotaro MORI
  • Patent number: 10770143
    Abstract: Memory systems and memory programming methods are described.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: September 8, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Makoto Kitagawa, Adam Johnson
  • Patent number: 10748613
    Abstract: Memory sense amplifiers and memory verification methods are described. According to one aspect, a memory sense amplifier includes a first input coupled with a memory element of a memory cell, wherein the memory element has different memory states at different moments in time, a second input configured to receive a reference signal, modification circuitry configured to provide a data signal at the first input from the memory element having a plurality of different voltages corresponding to respective ones of different memory states of the memory cell at the different moments in time, and comparison circuitry coupled with the modification circuitry and configured to compare the data signal and the reference signal at the different moments in time and to provide an output signal indicative of the memory state of the memory cell at the different moments in time as a result of the comparison to implement a plurality of verify operations of the memory states of the memory cell at the different moments in time.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: August 18, 2020
    Assignee: MIcron Technology, Inc.
    Inventors: Makoto Kitagawa, Kerry Tedrow
  • Patent number: 10706925
    Abstract: A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an intersection of a first wiring and a second wiring, and includes a variable resistance element having a resistance state that is variable between a first resistance state and a second resistance state. The writing circuit varies the variable resistance element from the first resistance state to the second resistance state, and thereby performs writing of data on the memory cell. The current controller controls a current and thereby limits the current to a predetermined limit current value. The current is caused to flow through the first wiring or the second wiring by the writing circuit upon performing of the writing of the data.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: July 7, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yotaro Mori, Makoto Kitagawa
  • Patent number: 10650762
    Abstract: During a drive period, luminance momentarily decreases when the value ?(A?B) is positive and momentarily increases when the value ?(A?B) is negative. When the luminance increases during a pause period in accordance with the balance in time constant between an alignment film and a liquid crystal material that are included in a pixel forming portion, primary and secondary parasitic capacitances are adjusted so as to set the value ?(A?B) to be negative.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 12, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Kitagawa, Hideki Fujimoto, Yusuke Nishihara
  • Patent number: 10622067
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20200098425
    Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.
    Type: Application
    Filed: May 11, 2018
    Publication date: March 26, 2020
    Inventors: YOTARO MORI, MAKOTO KITAGAWA, JUN OKUNO, HARUHIKO TERADA
  • Publication number: 20200020411
    Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a
    Type: Application
    Filed: March 13, 2018
    Publication date: January 16, 2020
    Inventors: HARUHIKO TERADA, MAKOTO KITAGAWA, YOSHIYUKI SHIBAHARA, YOTARO MORI
  • Publication number: 20190318782
    Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.
    Type: Application
    Filed: June 26, 2019
    Publication date: October 17, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino
  • Publication number: 20190311767
    Abstract: Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Wataru Otsuka, Takafumi Kunihiro, Tomohito Tsushima, Makoto Kitagawa, Jun Sumino, D. V. Nirmal Ramaswamy