Patents by Inventor Makoto Kitano

Makoto Kitano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6511857
    Abstract: In an electric characteristic testing process corresponding to a process of the semiconductor apparatus manufacturing processes, in order to test a large area of the electrode pad of the body to be tested in a lump, an electric characteristic testing is performed by pressing a testing structure provided with electrically independent projections having a number equal to a number of conductor portions to be tested formed on an area to be tested of a body to be tested to the body to be tested.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: January 28, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kono, Makoto Kitano, Hideo Miura, Hiroyuki Ota, Yoshishige Endo, Takeshi Harada, Masatoshi Kanamaru, Teruhisa Akashi, Atsushi Hosogane, Akihiko Ariga, Naoto Ban
  • Publication number: 20020182796
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Application
    Filed: June 17, 2002
    Publication date: December 5, 2002
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Publication number: 20020160185
    Abstract: A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).
    Type: Application
    Filed: May 6, 2002
    Publication date: October 31, 2002
    Inventors: Akira Nagai, Shuji Eguchi, Masahiko Ogino, Masanori Segawa, Toshiak Ishii, Nobutake Tsuyuno, Hiroyoshi Kokaku, Rie Hattori, Makoto Morishima, Ichiro Anjoh, Kunihiro Tsubosaki, Chuichi Miyazaki, Makoto Kitano, Mamoru Mita, Norio Okabe
  • Patent number: 6465876
    Abstract: A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.
    Type: Grant
    Filed: November 19, 1997
    Date of Patent: October 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Akihiro Yaguchi, Naotaka Tanaka, Takeshi Terasaki, Ichiro Anjoh, Ryo Haruta, Asao Nishimura, Junichi Saeki
  • Publication number: 20020140059
    Abstract: A semiconductor device includes a lead electrode connected to a lead, a case electrode having a projection part around its periphery, and a semiconductor chip having a rectification function and connected electrically between the lead electrode and the case electrode through connection members, wherein an electrically conductive plate is provided between the semiconductor chip and the lead electrode. Thereby, any of cracks is prevented from being generated in the semiconductor chip due to the mutual thermal deformation difference between the electrically conductive plate and the semiconductor chip which are electrically joined to each other through a joining member.
    Type: Application
    Filed: February 6, 2002
    Publication date: October 3, 2002
    Inventors: Misuk Yamazaki, Makoto Kitano
  • Patent number: 6455335
    Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: September 24, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Tetsuo Kumazawa, Makoto Kitano, Akihiko Ariga, Yuji Wada, Naoto Ban, Shuji Shibuya, Yasuhiro Motoyama, Kunio Matsumoto, Susumu Kasukabe, Terutaka Mori, Hidetaka Shigi, Takayoshi Watanabe
  • Patent number: 6448646
    Abstract: A semiconductor device-mounting construction including a semiconductor device having a plurality of electrodes formed on one main surface thereof. A printed circuit board having a writing pattern formed on one main surface thereof and a plurality of solder bumps interposed between the plurality of electrodes and the writing pattern to electrically connect the semiconductor device and the printed circuit board together. All of the voids, which are present in an interface of each of those of the plurality of solder bumps which are disposed closest to an outer peripheral edge of the semiconductor device, joined to the semiconductor device, are fine, and generally uniform in size.
    Type: Grant
    Filed: September 7, 2000
    Date of Patent: September 10, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Michiharu Honda
  • Publication number: 20020115877
    Abstract: The invention provides a novel silicon-containing compound having an oxidation potential of 0.3 to 1.5 V on the basis of a standard hydrogen electrode, wherein at least one alkoxy group is bonded to a silicon atom and at least one aromatic amine group is also bonded to the silicon atom.
    Type: Application
    Filed: February 5, 2002
    Publication date: August 22, 2002
    Applicant: Sumitomo Chemical Company, Limited
    Inventors: Masato Ueda, Isao Yahagi, Makoto Kitano
  • Publication number: 20020105781
    Abstract: There is disclosed an electronic apparatus having a water-cooling structure suited for a compact, thin design in which structure is brought about a liquid-circulating flow rate necessary and sufficient for an increased amount of heat occurring in a heat-generating element due to an improved processing performance of the electronic apparatus. In the electronic apparatus, a water-cooling jacket 8 is thermally connected to a heat-generating element 7, a heat-dissipating pipe 9 being thermally connected to a heat-dissipating metal sheet 9 provided at a rear panel of a display case 2, a cooling medium liquid being circulated between the water-cooling jacket 8 and the heat-dissipating pipe 9 by a liquid-moving device 11. The necessary and sufficient circulating flow rate and the necessary discharge pressure are determined by the relation between the upper limit temperature of the heat-generating element 7 and the limit amount of heat dissipation from the surface of the housing.
    Type: Application
    Filed: August 23, 2001
    Publication date: August 8, 2002
    Inventors: Shigeo Ohashi, Noriyuki Ashiwake, Takashi Naganawa, Makoto Kitano, Rintaro Minamitani, Yoshihiro Kondo, Tsuyoshi Nakagawa
  • Publication number: 20020075646
    Abstract: A liquid cooling system and a personal computer equipped with it, being suitable for a semiconductor device, etc, generating high heat therefrom and suppressing influences following corrosion upon an apparatus, thereby ensuring healthiness of the system as a whole, wherein it comprises: a pump for supplying cooling liquid; a heat receiving jacket being supplied with the cooling liquid, and for receiving heat generated from a heat generation body; a heat radiation pipe for radiating heat which is supplied by the cooling liquid passing through the heat receiving jacket; and a passage for circulating the cooling liquid passing through the heat radiation pipe into said pump, and the heat radiation pipe is made of material having corrosion resistance being higher than that of the heat receiving jacket.
    Type: Application
    Filed: August 6, 2001
    Publication date: June 20, 2002
    Inventors: Rintaro Minamitani, Makoto Kitano, Noriyuki Ashiwake, Shigeo Ohashi, Yoshihiro Kondo, Takashi Naganawa, Yuji Yoshitomi, Tsuyoshi Nakagawa
  • Publication number: 20020075645
    Abstract: A liquid cooling system for cooling a high heat generating body, such as a semiconductor element or the like, used in an electronic apparatus being small and thin in sizes, or a personal computer equipped with such the structure therein, comprising a ump of reciprocal movement type, a heat receiving jacket, a heat radiation pipe, and a connector pipe for connecting those parts with one another, wherein those are disposed to form a closed loop and are filled up with cooling liquid therein, and &Dgr;Vs is equal to or greater than &Dgr;Vp, defining that inner volume change when the pump emits pulsation therefrom is the &Dgr;Vp, that pressure caused accompanying with the volume change is P, and that volume change due to the pressure P in flow passage of the cooling liquid &Dgr;Vp other than portion of the pump.
    Type: Application
    Filed: August 6, 2001
    Publication date: June 20, 2002
    Inventors: Makoto Kitano, Takashi Naganawa, Yuji Yoshitomi, Rintaro Minamitani, Shigeo Ohashi, Noriyuki Ashiwake, Yoshihiro Kondo, Tsuyoshi Nakagawa
  • Patent number: 6403237
    Abstract: Provided is a high heat-resistant polymeric fluorescent substance having a divalent condensed polycyclic aromatic group of specific size having a bonding part at specific position shows fluorescence at a long wave length from orange to red, which is useful for fabricating an organic EL device having excellent properties by a coating method.
    Type: Grant
    Filed: June 8, 1999
    Date of Patent: June 11, 2002
    Assignee: Sumitomo Chemical Co., Ltd.
    Inventors: Takanobu Noguchi, Masamitsu Ishitobi, Makoto Kitano
  • Patent number: 6369258
    Abstract: The invention provides a novel silicon-containing compound having an oxidation potential of 0.3 to 1.5 V on the basis of a standard hydrogen electrode, wherein at least one alkoxy group is bonded to a silicon atom and at least one aromatic amine group is also bonded to the silicon atom. An organic electroluminescence device having excellent mechanical and electric contact between an electrode and an organic layer is also provided by treating the surface of an anode with using a surface-treating agent comprising the above silicon-containing compound.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: April 9, 2002
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masato Ueda, Isao Yahagi, Makoto Kitano
  • Publication number: 20020011661
    Abstract: A semiconductor chip has a semiconductor chip, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader.
    Type: Application
    Filed: April 3, 2001
    Publication date: January 31, 2002
    Inventors: Takeshi Terasaki, Hideo Miura, Chikara Nakajima, Makoto Kitano
  • Patent number: 6331730
    Abstract: A push-in type semiconductor chip has a semiconductor device, a support electrode body bonded to one of the end portions of the semiconductor chip and supported by, and fixed to, a heat spreader at a support fixing portion thereof, a lead electrode body bonded to the other end portion of the semiconductor chip and an insulating/sealing member disposed at the bond portion between the semiconductor chip and the support electrode body and at the bond portion between the semiconductor chip and the lead electrode body. The support electrode body includes a first portion having an outer diameter different from that of the support fixing portion at which the support electrode body is supported and fixed by the heat spreader. By setting a predetermined relationship between the outer diameters of the first portion and the support fixing portion, deformation and breakage of the semiconductor chip during assembly can be prevented.
    Type: Grant
    Filed: April 22, 1999
    Date of Patent: December 18, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Terasaki, Hideo Miura, Chikara Nakajima, Makoto Kitano
  • Patent number: 6326681
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 13, 2000
    Date of Patent: December 4, 2001
    Assignee: Hitachi, LTD
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6303982
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Grant
    Filed: January 30, 2001
    Date of Patent: October 16, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsuro Matsumoto
  • Patent number: 6297073
    Abstract: A semiconductor device, is provided will semiconductor chips having a plurality of electrodes for external connection, elastomer resin portions formed of an elastomer resin, which are bonded to the semiconductor chip excepting at least some of the plurality of electrodes, a tape layer of resin including tape wiring patterns on the surface thereof, a plurality of solder bumps for bonding the printed wiring pattern to the tape wiring patterns, leads for connecting the plurality of electrodes of the semiconductor chips to the tape wiring patterns, and seal resin for covering the leads and the plurality of electrodes which are connected by the leads. The elastomer resin has a modulus of transverse elasticity not less than 50 MPa and not more than 750 MPa.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: October 2, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Ryuji Kohno, Naotaka Tanaka, Akihiro Yaguchi, Tetsuo Kumazawa, Ichiro Anjoh, Hideki Tanaka, Asao Nishimura, Shuji Eguchi, Akira Nagai, Mamoru Mita
  • Publication number: 20010008302
    Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
    Type: Application
    Filed: January 30, 2001
    Publication date: July 19, 2001
    Inventors: Gen Murakami, Kunihiro Tsubosaki, Masahiro Ichitani, Kunihiko Nishi, Ichiro Anjo, Asao Nishimura, Makoto Kitano, Akihiro Yaguchi, Sueo Kawai, Masatsugu Ogata, Syuuji Eguchi, Hiroyoshi Kokaku, Masanori Segawa, Hiroshi Hozoji, Takashi Yokoyama, Noriyuki Kinjo, Aizo Kaneda, Junichi Saeki, Shozo Nakamura, Akio Hasebe, Hiroshi Kikuchi, Isamu Yoshida, Takashi Yamazaki, Kazuyoshi Oshima, Tetsurou Matsumoto
  • Patent number: RE37690
    Abstract: A lead frame and a semiconductor device wherein a through hole is formed in the center of a semiconductor chip-mounting surface of a chip pad at the center of the lead frame, the through hole being tapered or being one which corresponds to a surface area that is greater on the surface of the chip-mounting surface of the chip pad than on the surface of the side opposite to the chip-mounting surface thereof. This prevents the occurrence of cracks in the sealing plastic portion in the step of reflow soldering of the lead frame to the substrate.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: May 7, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kitano, Sueo Kawai, Asao Nishimura, Hideo Miura, Akihiro Yaguchi, Chikako van Koten nee Kitabayashi, Ichio Shimizu, Toshio Hatsuda, Toshinori Ozaki, Toshio Hattori, Souji Sakata