Abstract: By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.

Abstract: A process for preparing a single crystal silicon in accordance with the Czochralski method, is provided. More specifically, by quickly redueing the pull rate at least once during the growth of a neck portion of the single crystal silicon ingot, in order to change the melt/solid interface shape from a concave to a convex shape, the present process enables zero dislocation growth to be achieved in a large diameter neck within a comparably short neck length, such that large diameter ingots of substantial weight can be produced safely and at a high throughput.

Abstract: By eliminating a current of bit lines which is generated regularly by an off-leak current in memory cells, the number of memory cells per bit line is made to increase, large storage capacity of the memory cell array is achieved, and a semiconductor memory device capable of reducing a chip area is provided. In order to achieve it, provided is a source line potential control circuit for setting a source potential of transistors included in the memory cells being selected by row selection signals at a ground potential, and for setting a source potential of the transistors included in the memory cells being set as a non-selection state by the row selection signals at a power potential. A potential difference between sources and drains of the transistors included in the memory cells of the non-selection state is thereby reduced, and the leakage current is eliminated.

Abstract: In a semiconductor memory device, a first input end and a main bit line are precharged to a first voltage, and a sub-bit line is reset to a second voltage. Thereafter, a portion of the electric charge precharged in the first input end and the main bit line is redistributed to the sub-bit line. In this read method, until after potential inversion occurs between the main bit line and a complementary main bit line, the time of activating a selection gate is delayed from the times of activating a word line and a reference word line. Therefore, performance of an accurate sense operation can be secured, so that information can be accurately read from the memory cells without error.

Abstract: In a dynamic sensing-type nonvolatile semiconductor memory device of the invention, which employs a differential sense amplifier circuit, a memory cell is connected to a bit line using a word line and a reference memory cell is connected to an anti-bit line using a reference word line, the potential difference between the bit line and the anti-bit line is amplified by a sense amplifier, and when reading the data of the memory cell, at the start of data readout the bit lines are both precharged to a predetermined potential by a precharge circuit, and during and after precharging or only after precharging is finished, an identical amount of current is supplied to the bit line and the anti-bit line by a bit line current supply circuit.

Abstract: In a flash memory, a level shifter and a driver of a wordline driver are formed by MOS transistors having a low sustaining voltage, and a voltage control circuit for controlling a driver power supply voltage VPP is provided. The voltage control circuit holds VPP at a voltage LV which is below the sustaining voltage, when the logical state of the MOS transistors is changed. In addition, the voltage control circuit ramps up VPP from the low-level voltage LV to a voltage HV which is above the sustaining voltage, after the logical state of the MOS transistors has been changed. Further, the voltage control circuit ramps down VPP from the high-level voltage HV to the low-level voltage LV, before the logical state of the MOS transistors is changed next. Such arrangement enables even a wordline driver of the low-level voltage specification to handle not only low-level voltage but also high-level voltage without introducing any problems.

Abstract: A bus made up of a plurality of lines is interposed between a driver circuit on the transmitting end and a receiver circuit on the receiving end. An equalizer circuit includes multiple CMOS switches, each of which is connected between two adjacent ones of the bus lines. In changing data to be transmitted through the bus lines, first, the outputs of tristate buffers on the transmitting end should have high impedance and input buffers on the receiving end should be deactivated. Then, an equalize (EQ) signal is asserted, thereby activating the equalizer circuit. While the potential levels on the bus lines are being equalized, these bus lines are all electrically disconnected from a power supply. After the potential levels on the bus lines have been equalized in this manner, the EQ signal is negated and then normal signal transmission is carried out.

Abstract: The booster circuit includes a voltage reset circuit in a booster cell. The voltage reset circuit receives a gate voltage reset signal via a reset terminal of the booster circuit. The reset signal is asserted during abrupt change of the boosted voltage from high to low or during a restart after an instantaneous power interruption. The voltage reset circuit grounds the gate terminal of a charge-transfer transistor during the assertion of the gate voltage reset signal, to reset the gate potential of the charge-transfer transistor to the ground potential. By this resetting, normal boost operation is secured even in an event that a switching transistor remains cut-off because the amplitude of a boost clock signal is small due to use of low-voltage power supply.

Abstract: An electron-emitting device comprises a pair of opposing electrodes formed on a substrate, an electroconductive film having a fissure arranged between the pair of electrodes, and at least a film having a gap and containing carbon as a main ingredient, arranged at an end portion of the electroconductive film facing the fissure.

Abstract: A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information.

Abstract: In a semiconductor memory device, a first input end and a main bit line are precharged to a first voltage, and a sub-bit line is reset to a second voltage. Thereafter, a portion of the electric charge precharged in the first input end and the main bit line is redistributed to the sub-bit line. In this read method, until after potential inversion occurs between the main bit line and a complementary main bit line, the time of activating a selection gate is delayed from the times of activating a word line and a reference word line. Therefore, performance of an accurate sense operation can be secured, so that information can be accurately read from the memory cells without error.

Abstract: A Czochralski method of producing a single crystal silicon ingot having a uniform thermal history. In the process, the power supplied to the side heater is maintained substantially constant throughout the growth of the main body and end-cone of the ingot, while power supplied to a bottom heater is gradually increased during the growth of the second half of the main body and the end-cone. The present process enables an ingot to be obtained which yields wafers having fewer light point defects in excess of about 0.2 microns, while having improved gate oxide integrity.

Abstract: A semiconductor memory device 100 includes: a differential sense amplifier 9 having an input node 9a and an input node 9b, an information read section 110a, a reference section 110b, and a control section 140. The information read section 110a includes: a main bit line MBL coupled to the input node 9a; a select gate 4a; a sub-bit line SBL which is coupled to the main bit line MBL via the select gate 4a; a memory cell 1 which is coupled to the sub-bit line SBL and which is selectively activated in accordance with a voltage on a word line WL; a precharge section 120a for precharging the input node 9a and the main bit line MBL to a supply voltage Vdd; and a reset section 130b for resetting the sub-bit line SBL to a ground voltage Vss.

Abstract: A semiconductor memory device 100 includes: a differential sense amplifier 9 having an input node 9a and an input node 9b, an information read section 110a, a reference section 110b, and a control section 140. The information read section 110a includes: a main bit line MBL coupled to the input node 9a; a select gate 4a; a sub-bit line SBL which is coupled to the main bit line MBL via the select gate 4a; a memory cell 1 which is coupled to the sub-bit line SBL and which is selectively activated in accordance with a voltage on a word line WL: a precharge section 120a for precharging the input node 9a and the main bit line MBL to a supply voltage Vdd; and a reset section 130b for resetting the sub-bit line SBL to a ground voltage Vss.

Abstract: A pressure-sensitive adhesive composition, wherein the storage elastic modulus [G′] at room temperature is at least 2×106 dyne/cm2 and the adhesive strength at room temperature is 1 kg/20 mm width or higher. Preferably, a pressure-sensitive adhesive composition comprising a polymer having a polycarbonate structure having a repeating unit represented by the following formula wherein R represents a straight chain or branched hydrocarbon group having from 2 to 20 carbon atoms, a pressure-sensitive adhesive sheet, a sealing material, a reinforcing sheet, and a pressure-sensitive sheet for printing, each having the pressure-sensitive adhesive composition.

Abstract: To read data stored on a memory cell transistor with a floating gate, a flash memory uses: a single-gate reference transistor; a differential sense amplifier; and a gate voltage generator for generating a gate voltage for the reference transistor. The gate voltage generator includes: a dummy cell transistor, which has the same structure as the memory cell transistor and has been turned ON; a current mirror for creating a current proportional to a drain current of the dummy cell transistor; an NMOS transistor for generating a gate voltage for the reference transistor in accordance with the current created by the current mirror; and a voltage hold circuit for holding the gate voltage generated. Even if temperature or fabricating process conditions have changed, this construction ensures accurate and high-speed read operation.

Abstract: Four memory banks (10 to 13), each having a hierarchical word line structure, are provided. If a particular mode for one of the memory banks is specified by a control packet (PKT), a mode recognizer (15) produces the leading edges of change-of-sub-word enable (SEN0-3) and change-of-column enable (CEN-3) signals with the logical level of change-of-main-word enable (MEN0-3) signal fixed. This is done to make activated ones of sub-word and column select lines changeable in each of the memory banks with the same main word line still selected. In this manner, the row access speeds increase for the respective memory banks.

Abstract: A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information.

Abstract: A bus made up of a plurality of lines is interposed between a driver circuit on the transmitting end and a receiver circuit on the receiving end. An equalizer circuit includes multiple CMOS switches, each of which is connected between two adjacent ones of the bus lines. In changing data to be transmitted through the bus lines, first, the outputs of tristate buffers on the transmitting end should have high impedance and input buffers on the receiving end should be deactivated. Then, an equalize (EQ) signal is asserted, thereby activating the equalizer circuit. While the potential levels on the bus lines are being equalized, these bus lines are all electrically disconnected from a power supply. After the potential levels on the bus lines have been equalized in this manner, the EQ signal is negated and then normal signal transmission is carried out.

Abstract: In a flash memory, a level shifter and a driver of a wordline driver are formed by MOS transistors having a low sustaining voltage, and a voltage control circuit for controlling a driver power supply voltage VPP is provided. The voltage control circuit holds VPP at a voltage LV which is below the sustaining voltage, when the logical state of the MOS transistors is changed. In addition, the voltage control circuit ramps up VPP from the low-level voltage LV to a voltage HV which is above the sustaining voltage, after the logical state of the MOS transistors has been changed. Further, the voltage control circuit ramps down VPP from the high-level voltage HV to the low-level voltage LV, before the logical state of the MOS transistors is changed next. Such arrangement enables even a wordline driver of the low-level voltage specification to handle not only low-level voltage but also high-level voltage without introducing any problems.