Patents by Inventor Makoto Ogasawara

Makoto Ogasawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220174998
    Abstract: A solid paste composition for cooking, which has elasticity, suppresses a rubber-like texture, and has a good chewy texture. The solid paste composition satisfies containing 2.0 mass % or more of an insoluble dietary fiber in terms of dry mass, 15 mass % or more of a starch in terms of dry mass, and 5.5 mass % or more of a protein in terms of dry mass. The solid paste composition further satisfies at least either of the ratio of the number of CBB-stained sites having an area of at least 200 ?m2 and a roundness coefficient of at least 0.3, to the number of CBB-stained sites being 3% or more, and the ratio of the total area of CBB-stained sites having an area of at least 200 ?m2 and a roundness coefficient of at least 0.3, to the image area of a cross-section of the composition being 0.3% or more.
    Type: Application
    Filed: February 28, 2022
    Publication date: June 9, 2022
    Applicant: MIZKAN HOLDINGS CO., LTD.
    Inventors: Makoto Suzuki, Kiyoshi Endo, Yusuke Tange, Naruhiro Hibi, Takuya Nakayama, Yasushi Ogasawara, Yukiko Kawamura, Junichiro Ihara
  • Patent number: 10859590
    Abstract: According to one embodiment, an automatic analyzing apparatus includes a liquid tank, a first pump, a dispensing probe, and a thermal exchanger. The liquid tank stores a first liquid. The first pump pressurizes and sends the first liquid supplied from the liquid tank. The dispensing probe uses the first liquid that is sent out from the first pump as a pressure transmitting medium. The thermal exchanger exchanges heat between an atmosphere in the automatic analyzing apparatus and the first liquid in at least a part of a first flow path connecting the first pump to the liquid tank.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: December 8, 2020
    Assignee: Canon Medical Systems Corporation
    Inventors: Kenji Yamasaki, Takehiko Onuma, Makoto Ogasawara, Hiroko Takayama, Reiko Maruyama
  • Patent number: 10651094
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: May 12, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki Aono, Tetsuya Yoshida, Makoto Ogasawara, Shinichi Okamoto
  • Patent number: 10438861
    Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: October 8, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hideki Aono, Makoto Ogasawara, Naohito Suzumura, Tetsuya Yoshida
  • Publication number: 20190198402
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Inventors: Hideki AONO, Tetsuya YOSHIDA, Makoto OGASAWARA, Shinichi OKAMOTO
  • Patent number: 10211620
    Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Kan Takeuchi, Mitsuhiko Igarashi, Makoto Ogasawara
  • Publication number: 20180267070
    Abstract: According to one embodiment, an automatic analyzing apparatus includes a liquid tank, a first pump, a dispensing probe, and a thermal exchanger. The liquid tank stores a first liquid. The first pump pressurizes and sends the first liquid supplied from the liquid tank. The dispensing probe uses the first liquid that is sent out from the first pump as a pressure transmitting medium. The thermal exchanger exchanges heat between an atmosphere in the automatic analyzing apparatus and the first liquid in at least a part of a first flow path connecting the first pump to the liquid tank.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 20, 2018
    Applicant: Canon Medical Systems Corporation
    Inventors: Kenji Yamasaki, Takehiko Onuma, Makoto Ogasawara, Hiroko Takayama, Reiko Maruyama
  • Publication number: 20170092555
    Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 30, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Hideki AONO, Makoto OGASAWARA, Naohito SUZUMURA, Tetsuya YOSHIDA
  • Publication number: 20170063075
    Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.
    Type: Application
    Filed: July 22, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Kan TAKEUCHI, Mitsuhiko IGARASHI, Makoto OGASAWARA
  • Publication number: 20160141289
    Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.
    Type: Application
    Filed: November 6, 2015
    Publication date: May 19, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hideki AONO, Tetsuya YOSHIDA, Makoto OGASAWARA, Shinichi OKAMOTO
  • Patent number: 7789077
    Abstract: To prevent dew condensation in a crankcase in a lower part of the crankcase, wherein an oil pan is an integral part of an internal combustion engine, to prevent lubricating oil from being diluted. A crankcase cover covers at least an oil pan out of a crankcase and is provided to the bottom of the crankcase. A heat insulating material is provided between the crankcase and the crankcase cover. A cooling fluid passage for providing a circulation to cool a cylinder or a cylinder head is provided between the crankcase and the crankcase cover. A passage at least one end of which reaches a cylinder head from a crankcase via a cylinder block forms at least a part of a blowby gas passage, is directly provided to the crankcase, the cylinder block and the cylinder head. A flow control valve is arranged in the cylinder block or the cylinder head.
    Type: Grant
    Filed: April 10, 2007
    Date of Patent: September 7, 2010
    Assignee: Honda Motor Co., Ltd.
    Inventors: Kazunori Igarashi, Makoto Ogasawara
  • Publication number: 20070245983
    Abstract: To prevent dew condensation in a crankcase in a lower part of the crankcase, wherein an oil pan is an integral part of an internal combustion engine, to prevent lubricating oil from being diluted. A crankcase cover covers at least an oil pan out of a crankcase and is provided to the bottom of the crankcase. A heat insulating material is provided between the crankcase and the crankcase cover. A cooling fluid passage for providing a circulation to cool a cylinder or a cylinder head is provided between the crankcase and the crankcase cover. A passage at least one end of which reaches a cylinder head from a crankcase via a cylinder block forms at least a part of a blowby gas passage, is directly provided to the crankcase, the cylinder block and the cylinder head. A flow control valve is arranged in the cylinder block or the cylinder head.
    Type: Application
    Filed: April 10, 2007
    Publication date: October 25, 2007
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Kazunori Igarashi, Makoto Ogasawara
  • Patent number: 6949387
    Abstract: A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: September 27, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Miura, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto
  • Patent number: 6894334
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: May 17, 2005
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20040214355
    Abstract: A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.
    Type: Application
    Filed: July 25, 2003
    Publication date: October 28, 2004
    Inventors: Hideo Miura, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto, Jun Murata, Noriaki Okamoto
  • Publication number: 20030189255
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Application
    Filed: March 3, 2003
    Publication date: October 9, 2003
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Patent number: 6620704
    Abstract: A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: September 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hideo Miura, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto
  • Patent number: 6573546
    Abstract: A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kiyonori Ohyu, Makoto Ohkura, Aritoshi Sugimoto, Yoshitaka Tadaki, Makoto Ogasawara, Masashi Horiguchi, Norio Hasegawa, Shinichi Fukada
  • Patent number: 6548847
    Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: April 15, 2003
    Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.
    Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
  • Publication number: 20020093060
    Abstract: A width of a circuit device isolation region and a width of a device region formed on a semiconductor substrate are determined in such a manner as to satisfy a condition which prevents the occurrence of dislocation due to thermal oxidation for forming the isolation region. A semiconductor device can be fabrication which includes a semiconductor substrate, a plurality of circuit regions formed on a device formation region in the semiconductor substrate and having a width of 0.1 to 125 &mgr;m and device isolation regions so formed on the semiconductor substrate as to isolate a plurality of circuit regions from one another and having a width of 0.05 to 2.5 &mgr;m, and wherein a ratio of the width of the device isolation region to the width of a plurality of circuit regions adjacent to the device isolation region is from 2 to 50.
    Type: Application
    Filed: June 29, 2001
    Publication date: July 18, 2002
    Inventors: Hideo Miura, Makoto Ogasawara, Hiroo Masuda, Jun Murata, Noriaki Okamoto, Yasunobu Tanizaki, Eiji Wakimoto, Shinji Sakata