Patents by Inventor Makoto Saen

Makoto Saen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9337838
    Abstract: In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: May 10, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saen, Takeshi Sakata, Masashi Ohkawa, Yusuke Kanno
  • Patent number: 9144908
    Abstract: A manipulator device has an arm portion and a hand portion The hand portion includes one or more finger portions that manipulate a target object. Each finger portion includes a slip sensor and multiple contact sensors, with at least one contact sensor at a position proximate to the slip sensor and at least another contact sensor at a position remote from the slip sensor. When the contact sensors at the positions remote from the slip sensor detect contact of the target object and the contact sensors arranged at the positions proximate to the slip sensors do not detect contact, a position of the finger portion is moved by a distance corresponding to the distance between the contact sensors detecting contact of the target object and the contact sensors arranged at the positions proximate to the slip such that a detecting position of the slip sensor is coincident with a position of the target object.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 29, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saen, Kiyoto Ito, Yoshimitsu Yanagawa, Tomomi Takahashi
  • Publication number: 20150236696
    Abstract: In a device including a programmable circuit, the programmable circuit is connected to a non-volatile memory in which configuration information is stored, and another memory having a faster reading speed than the non-volatile memory, and the programmable circuit includes a configuration memory control circuit, and a signal line group for performing reading with respect to the other memory such as a volatile memory and an embedded memory from the non-volatile memory by the configuration memory control circuit, and copies a part of circuit configuration information which is required to be subjected to fast restoration from failure into the other memory.
    Type: Application
    Filed: January 9, 2015
    Publication date: August 20, 2015
    Inventors: MAKOTO SAEN, TAKESHI SAKATA, MASASHI OHKAWA, YUSUKE KANNO
  • Publication number: 20140148951
    Abstract: A manipulator device has an arm portion and a hand portion The hand portion includes one or more finger portions that manipulate a target object. Each finger portion includes a slip sensor and multiple contact sensors, with at least one contact sensor at a position proximate to the slip sensor and at least another contact sensor at a position remote from the slip sensor. When the contact sensors at the positions remote from the slip sensor detect contact of the target object and the contact sensors arranged at the positions proximate to the slip sensors do not detect contact, a position of the finger portion is moved by a distance corresponding to the distance between the contact sensors detecting contact of the target object and the contact sensors arranged at the positions proximate to the slip such that a detecting position of the slip sensor is coincident with a position of the target object.
    Type: Application
    Filed: April 18, 2012
    Publication date: May 29, 2014
    Inventor: Makoto Saen
  • Patent number: 8698140
    Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: April 15, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Kiyoto Ito, Takanobu Tsunoda, Makoto Saen
  • Patent number: 8508968
    Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: August 13, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saen, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi
  • Patent number: 8482997
    Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
    Type: Grant
    Filed: February 5, 2012
    Date of Patent: July 9, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
  • Publication number: 20130079905
    Abstract: In a human-operated working machine system made up of a working machine including an actuator and an operating device, various operations for target objects having various hardnesses and shapes are achieved at a speed not giving stress to an operator. To this end, the working machine has a control structure in which a control program corresponding to an action content is executed with both of displacement information with respect to the working machine inputted from the operating device and information from a sensor of the working machine being taken as inputs. Furthermore, the operating device has a simulator that predicts an action of the working machine so as to quickly provide image information and tactile information regarding the action of the working machine to the operator.
    Type: Application
    Filed: June 3, 2010
    Publication date: March 28, 2013
    Applicant: HITACHI, LTD.
    Inventors: Makoto Saen, Kiyoto Ito
  • Patent number: 8350595
    Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Masafumi Onouchi
  • Publication number: 20120280231
    Abstract: It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop (31b) by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.
    Type: Application
    Filed: March 15, 2010
    Publication date: November 8, 2012
    Inventors: Kiyoto Ito, Takanobu Tsunoda, Makoto Saen
  • Publication number: 20120217620
    Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 30, 2012
    Inventors: Makoto SAEN, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi
  • Patent number: 8253227
    Abstract: A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: August 28, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Kenichi Osada, Makoto Saen, Futoshi Furuta
  • Patent number: 8242589
    Abstract: In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 14, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saen, Kenichi Osada, Kiyoto Ito
  • Publication number: 20120187993
    Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
    Type: Application
    Filed: April 3, 2012
    Publication date: July 26, 2012
    Inventors: Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Masafumi Onouchi
  • Publication number: 20120135548
    Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
    Type: Application
    Filed: February 5, 2012
    Publication date: May 31, 2012
    Inventors: SATORU HANZAWA, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen
  • Patent number: 8183899
    Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: May 22, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Masafumi Onouchi
  • Patent number: 8184463
    Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.
    Type: Grant
    Filed: December 13, 2009
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saen, Kenichi Osada, Masanao Yamaoka, Tomonori Sekiguchi
  • Patent number: 8148814
    Abstract: In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Futoshi Furuta, Kenichi Osada, Makoto Saen
  • Patent number: 8150578
    Abstract: In a vehicle electronic system including a plurality of LSI boards, LSIS which cannot control a user interface such as image or audio directly issue a command for notifying a vehicle occupant of its own information via networks and an information control LSI receives the request to output a message. A mechanism for setting priority of processings regarding LSI status information notification to be lower than that of an apparatus control processing is provided in each of LSIs and networks so that real-time property of the apparatus control processing is maintained. In order to reduce network load regarding the LSI status information notification, a message content itself is stored in a memory in a vehicle information processing unit previously so that only an ID for identifying the message content is transmitted.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: April 3, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Saen, Kenichi Osada, Shigeru Oho
  • Patent number: 8130575
    Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: March 6, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Satoru Hanzawa, Hitoshi Kume, Motoyasu Terao, Tomonori Sekiguchi, Makoto Saen