Abstract: Provided is a laminate that can be pre-trimmed and can eliminate the need for a post-processing step. A laminate includes a decorative layer, an adhesive layer, and a support layer laminated in this order. The support layer includes two or more kinds of materials having different melting points including a material having a relatively low melting point and a material having a relatively high melting point.

Abstract: First and second buffer regions and an n?-type drift region are sequentially formed by epitaxial growth on an n+-type starting substrate. An impurity concentration of the first buffer region is higher than that of the n?-type drift region and lower than that of the n+-type starting substrate. An impurity concentration of the second buffer region is higher than that of the first buffer region and continuously increases by a first impurity concentration gradient from a first gradient changing point toward the n?-type drift region to a second gradient changing point toward the first buffer region; continuously decreases by a second impurity concentration gradient from the first gradient changing point to a first interface; and continuously decreases by a third impurity concentration gradient from the second gradient changing point to a second interface. The second impurity concentration gradient is lower than the third impurity concentration gradient.

Abstract: An n+-type SiC substrate constituting an n+-type drain region contains a concentration of nitrogen, which is a donor, within a predetermined range (predetermined impurity concentration of the n+-type drain region) and, as impurities other than the nitrogen, contains boron, aluminum, and titanium such that a sum of respective concentrations of the boron, aluminum, and titanium is an amount that does not affect the n-type impurity concentration of the n+-type SiC substrate (impurity concentration of the n+-type drain region). The boron, aluminum, and titanium in the n+-type SiC substrate function as a lifetime killer of majority carriers. The boron concentration of the n+-type SiC substrate is in a range of 5×1016/cm3 to 1×1017/cm3. The aluminum concentration and the concentration of the titanium concentration of the n+-type SiC substrate are each within a range of 1×1016/cm3 to 5×1016/cm3.

Abstract: A body diode is energized by inputting a BD energization pulse signal having a predetermined cycle. At the start of energization of the body diode and immediately before termination thereof, an ON signal of a Von measurement pulse signal is input to a high-temperature semiconductor chip at a timing different from that of an ON signal of the BD energization pulse signal, thereby passing a drain-source current through a MOSFET, and a drain-source voltage is measured. Thereafter, energization of the body diode is terminated. At room temperature before and after the energization of the body diode, the drain-source voltage is measured by inputting the ON signal of the Von measurement pulse signal. A semiconductor chip for which a fluctuation amount of the drain-source voltage at a high temperature and a fluctuation amount of the drain-source voltage at room temperature are within predetermined ranges is determined to be a conforming product.

Abstract: A semiconductor device includes a semiconductor device provided on a semiconductor substrate and an ohmic electrode provided on a back surface of the semiconductor device and containing a nickel silicide and a molybdenum carbide, or the nickel silicide and a titanium carbide. The ohmic electrode is configured by first regions where a silicide is thick and second regions where the silicide is thin; a ratio of an arithmetic area of the second regions to an arithmetic area of the ohmic electrode is in a range from 10% to 30% in a plan view.

Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.

Abstract: A silicon carbide semiconductor device, including a semiconductor substrate containing silicon carbide, a bonding wire, and a surface electrode of an aluminum alloy containing silicon, the surface electrode being provided on a surface of the semiconductor substrate, and having a joint portion to which the bonding wire is bonded. The surface electrode has a plurality of silicon nodules formed therein, which include a number of the silicon nodules formed in the joint portion. One of the number of the silicon nodules is of a dendrite structure, and is included at an area percentage of at least 10% relative to a total area of the number of the silicon nodules in the joint portion.

Abstract: Back-surface roughness of a back surface of a silicon carbide semiconductor device having a MOS gate structure in a first region that is a region within 30 ?m of a cross section (lateral surface) of the device is at most 4 ?m while the back-surface roughness in a second region other than the first region is at most 2 ?m, the back surface of the silicon carbide semiconductor device is the back surface of the second electrode. In a method of manufacture, the back-surface roughness of the device is specified to meet a predetermined condition. Then, ON voltages of the device before and after a forward current is passed through body diodes of the device are measured, and a rate of change of the ON voltage while the forward current is passed through body diodes is calculated, and then the device having a calculated rate of change less than 3% is identified.

Abstract: A body diode is energized by inputting a BD energization pulse signal having a predetermined cycle. At the start of energization of the body diode and immediately before termination thereof, an ON signal of a Von measurement pulse signal is input to a high-temperature semiconductor chip at a timing different from that of an ON signal of the BD energization pulse signal, thereby passing a drain-source current through a MOSFET, and a drain-source voltage is measured. Thereafter, energization of the body diode is terminated. At room temperature before and after the energization of the body diode, the drain-source voltage is measured by inputting the ON signal of the Von measurement pulse signal. A semiconductor chip for which a fluctuation amount of the drain-source voltage at a high temperature and a fluctuation amount of the drain-source voltage at room temperature are within predetermined ranges is determined to be a conforming product.

Abstract: A portion of a source pad is exposed in an opening of a passivation film. In the exposed portion of the source pad, a wiring region in which a package wiring member is to be bonded and a probe region that is a region different from the wiring region are provided. The probe region has a probe mark of a probe for an energization inspection. An area of the probe mark that overlaps the wiring region is at most 30% of an entire area of the wiring region in a plan view of the silicon carbide semiconductor device.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.

Abstract: A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region includes a first portion that contains arsenic and a second portion that contains phosphorous.

Abstract: A silicon carbide semiconductor device including a semiconductor substrate containing silicon carbide, a contact electrode, which is a silicide layer containing nickel, provided on a surface of the semiconductor substrate and forming an ohmic contact with the semiconductor substrate, and a metal connection layer provided on a surface of the contact electrode. The metal connection layer has a stacked structure in which on the surface of the contact electrode, a titanium layer, a nickel layer, and a gold layer are sequentially stacked. The titanium layer includes a carbon diffusion layer formed along an interface between the titanium layer and the contact electrode, a concentration of carbon being higher in the carbon diffusion layer than in a portion of the titanium layer other than the carbon diffusion layer. The titanium layer, the nickel layer and the gold layer have thicknesses of 100 nm to 300 nm, 1000 nm to 1500 nm, and 20 nm to 200 nm, respectively.

Abstract: A semiconductor device includes a semiconductor device provided on a semiconductor substrate and an ohmic electrode provided on a back surface of the semiconductor device and containing a nickel silicide and a molybdenum carbide, or the nickel silicide and a titanium carbide. The ohmic electrode is configured by first regions where a silicide is thick and second regions where the silicide is thin; a ratio of an arithmetic area of the second regions to an arithmetic area of the ohmic electrode is in a range from 10% to 30% in a plan view.

Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.

Abstract: A p-type base region is configured by a p?-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.

Abstract: A MOS-gate silicon carbide semiconductor device has an interlayer insulating film that covers a gate electrode and that has a 2-layer structure in which a NSG film and a BPSG film are sequentially stacked. The BPSG film has a boron concentration in a range from 4.5 mol % to 8.0 mol %. The BPSG film has a phosphorus concentration in a range from 1.0 mol % to 3.5 mol %. The NSG film has a thickness in a range from 50 nm to 400 nm. The BPSG film has a thickness in a range from 400 nm to 800 nm. A distance from the gate insulating film to the BPSG film is at most 100 nm at a portion where the gate insulating film and the BPSG film oppose each other across the NSG film.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.

Abstract: A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.

Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.