Patents by Inventor Makoto Utsumi

Makoto Utsumi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10886398
    Abstract: A MOS-gate silicon carbide semiconductor device has an interlayer insulating film that covers a gate electrode and that has a 2-layer structure in which a NSG film and a BPSG film are sequentially stacked. The BPSG film has a boron concentration in a range from 4.5 mol % to 8.0 mol %. The BPSG film has a phosphorus concentration in a range from 1.0 mol % to 3.5 mol %. The NSG film has a thickness in a range from 50 nm to 400 nm. The BPSG film has a thickness in a range from 400 nm to 800 nm. A distance from the gate insulating film to the BPSG film is at most 100 nm at a portion where the gate insulating film and the BPSG film oppose each other across the NSG film.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: January 5, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yoshiyuki Sakai
  • Publication number: 20200343345
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide semiconductor layer of the first conductivity type, a second silicon carbide semiconductor layer of a second conductivity type, a first silicon carbide semiconductor region of the first conductivity type, a trench, and a gate electrode on a gate insulating film. Between the gate insulating film and any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region is an interface section where a concentration of oxygen varies, the interface section having closer to the gate insulating film than to the any one among the first silicon carbide semiconductor layer, the second silicon carbide semiconductor layer, and the first silicon carbide semiconductor region, a region where a rate of increase of the oxygen included in the interface section is greatest.
    Type: Application
    Filed: March 25, 2020
    Publication date: October 29, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Tsuyoshi ARAOKA
  • Patent number: 10790373
    Abstract: A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: September 29, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yoshiyuki Sakai
  • Patent number: 10756200
    Abstract: A silicon carbide semiconductor element includes n-type silicon carbide epitaxial layers formed on an n+-type silicon carbide semiconductor substrate, plural p base layers selectively formed in surfaces of the silicon carbide epitaxial layers, a p-type silicon carbide epitaxial layer formed in the silicon carbide epitaxial layer, and a trench penetrating at least the silicon carbide epitaxial layer. The silicon carbide semiconductor element also includes, in a portion of the silicon carbide epitaxial layer, a mesa portion exposing the p base layer. The silicon carbide semiconductor element further includes, between consecutive mesa side faces of the mesa portion, a flat portion substantially parallel to the silicon carbide substrate. The remaining thickness of the exposed p base layer is larger than 0.5 ?m and smaller than 1.0 ?m.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: August 25, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Kenji Fukuda, Shinsuke Harada, Masanobu Iwaya
  • Publication number: 20200212183
    Abstract: A p-type base region is configured by a p?-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.
    Type: Application
    Filed: October 22, 2019
    Publication date: July 2, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Tsuyoshi ARAOKA
  • Publication number: 20200152594
    Abstract: A silicon carbide semiconductor device including a semiconductor substrate containing silicon carbide, a contact electrode, which is a silicide layer containing nickel, provided on a surface of the semiconductor substrate and forming an ohmic contact with the semiconductor substrate, and a metal connection layer provided on a surface of the contact electrode. The metal connection layer has a stacked structure in which on the surface of the contact electrode, a titanium layer, a nickel layer, and a gold layer are sequentially stacked. The titanium layer includes a carbon diffusion layer formed along an interface between the titanium layer and the contact electrode, a concentration of carbon being higher in the carbon diffusion layer than in a portion of the titanium layer other than the carbon diffusion layer. The titanium layer, the nickel layer and the gold layer have thicknesses of 100 nm to 300 nm, 1000 nm to 1500 nm, and 20 nm to 200 nm, respectively.
    Type: Application
    Filed: September 27, 2019
    Publication date: May 14, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Yoshiyuki SAKAI
  • Publication number: 20200123110
    Abstract: The present invention provides low hygroscopic forms of aripiprazole and processes for the preparation thereof which will not convert to a hydrate or lose their original solubility even when a medicinal preparation containing the anhydrous aripiprazole crystals is stored for an extended period.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Inventors: Takuji BANDO, Satoshi AOKI, Junichi KAWASAKI, Makoto ISHIGAMI, Youichi TANIGUCHI, Tsuyoshi YABUUCHI, Kiyoshi FUJIMOTO, Yoshihiro NISHIOKA, Noriyuki KOBAYASHI, Tsutomu FUJIMURA, Masanori TAKAHASHI, Kaoru ABE, Tomonori NAKAGAWA, Koichi SHINHAMA, Naoto UTSUMI, Michiaki TOMINAGA, Yoshihiro OOI, Shohei YAMADA, Kenji TOMIKAWA
  • Patent number: 10600872
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: March 24, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Fumikazu Imai
  • Patent number: 10580870
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 3, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuhiko Oonishi, Fumikazu Imai
  • Publication number: 20190378921
    Abstract: A MOS-gate silicon carbide semiconductor device has an interlayer insulating film that covers a gate electrode and that has a 2-layer structure in which a NSG film and a BPSG film are sequentially stacked. The BPSG film has a boron concentration in a range from 4.5 mol % to 8.0 mol %. The BPSG film has a phosphorus concentration in a range from 1.0 mol % to 3.5 mol %. The NSG film has a thickness in a range from 50 nm to 400 nm. The BPSG film has a thickness in a range from 400 nm to 800 nm. A distance from the gate insulating film to the BPSG film is at most 100 nm at a portion where the gate insulating film and the BPSG film oppose each other across the NSG film.
    Type: Application
    Filed: April 15, 2019
    Publication date: December 12, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Yoshiyuki SAKAI
  • Patent number: 10439060
    Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 8, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Shinsuke Harada, Makoto Utsumi, Yasuhiko Oonishi
  • Publication number: 20190225584
    Abstract: The present invention provides low hygroscopic forms of aripiprazole and processes for the preparation thereof which will not convert to a hydrate or lose their original solubility even when a medicinal preparation containing the anhydrous aripiprazole crystals is stored for an extended period.
    Type: Application
    Filed: October 24, 2018
    Publication date: July 25, 2019
    Inventors: Takuji BANDO, Satoshi AOKI, Junichi KAWASAKI, Makoto ISHIGAMI, Youichi TANIGUCHI, Tsuyoshi YABUUCHI, Kiyoshi FUJIMOTO, Yoshihiro NISHIOKA, Noriyuki KOBAYASHI, Tsutomu FUJIMURA, Masanori TAKAHASHI, Kaoru ABE, Tomonori NAKAGAWA, Koichi SHINHAMA, Naoto UTSUMI, Michiaki TOMINAGA, Yoshihiro OOI, Shohei YAMADA, Kenji TOMIKAWA
  • Patent number: 10319824
    Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10304930
    Abstract: In forming an n+-type source region in a surface region of a p-type base layer by ion implantation, ion implantation of arsenic and ion implantation of nitrogen are sequentially performed. The ion implantation of nitrogen is performed by acceleration energy higher than that of the ion implantation of arsenic. The n+-type source region has an arsenic concentration profile and a nitrogen concentration profile formed to overlap each other at a different depth from the front surface of the base substrate. A peak of the nitrogen concentration profile is positioned deeper than a peak of the arsenic concentration profile from the front surface of the base substrate. The overall impurity concentration distribution of the n+-type source region is a concentration profile that is formed by summing the arsenic concentration profile and the nitrogen concentration profile with each other and whose diffusion depth is large.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: May 28, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Makoto Utsumi, Yasuhiko Oonishi
  • Publication number: 20190157398
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.
    Type: Application
    Filed: January 4, 2019
    Publication date: May 23, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Yasuhiko OONISHI, Fumikazu IMAI
  • Publication number: 20190140092
    Abstract: A silicon carbide semiconductor device includes: a drift region of a first conductivity type; a base region of a second conductivity type disposed on the drift region; a main electrode contact region of the first conductivity type selectively embedded in a top of the base region at a higher impurity density than the drift region; a trench having a round part on a top surface side of the main electrode contact region to a level that is shallower than a depth of the main electrode contact region, the trench going from the round part through the base region and having a bottom that reaches the drift region; and an insulated gate structure provided on an inner side of the trench. A smallest radius of curvature of the round part is greater than a relatively high impurity region of the main electrode contact region.
    Type: Application
    Filed: October 9, 2018
    Publication date: May 9, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Makoto UTSUMI, Yoshiyuki SAKAI
  • Publication number: 20190115439
    Abstract: A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.
    Type: Application
    Filed: September 6, 2018
    Publication date: April 18, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Makoto UTSUMI, Yoshiyuki SAKAI
  • Patent number: 10263082
    Abstract: A gate trench of a MOS gate formed in the front surface of a silicon carbide substrate includes a first portion that includes the bottom surface of the gate trench, a second portion that is connected to the substrate front surface side of the first portion, and a third portion that is connected to the substrate front surface side of the second portion. In the third portion of the gate trench, an n+ source region is exposed along the sidewalls. The width of the third portion of the gate trench is greater than the widths of the first and second portions and of the gate trench. Upper corners of the gate trench smoothly connect the sidewalls to the substrate front surface. The thickness of a gate insulating film smoothly connected along the bottom surface and sidewalls of the gate trench is substantially uniform over the entire inner wall surface of the gate trench.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Akimasa Kinoshita
  • Publication number: 20180366574
    Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.
    Type: Application
    Filed: May 30, 2018
    Publication date: December 20, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki OHSE, Shinsuke HARADA, Makoto UTSUMI, Yasuhiko OONISHI
  • Publication number: 20180301536
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 18, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Yasuhiko OONISHI, Fumikazu IMAI