Abstract: A p-type base region is configured by a p?-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.

Abstract: A silicon carbide semiconductor device including a semiconductor substrate containing silicon carbide, a contact electrode, which is a silicide layer containing nickel, provided on a surface of the semiconductor substrate and forming an ohmic contact with the semiconductor substrate, and a metal connection layer provided on a surface of the contact electrode. The metal connection layer has a stacked structure in which on the surface of the contact electrode, a titanium layer, a nickel layer, and a gold layer are sequentially stacked. The titanium layer includes a carbon diffusion layer formed along an interface between the titanium layer and the contact electrode, a concentration of carbon being higher in the carbon diffusion layer than in a portion of the titanium layer other than the carbon diffusion layer. The titanium layer, the nickel layer and the gold layer have thicknesses of 100 nm to 300 nm, 1000 nm to 1500 nm, and 20 nm to 200 nm, respectively.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.

Abstract: A MOS-gate silicon carbide semiconductor device has an interlayer insulating film that covers a gate electrode and that has a 2-layer structure in which a NSG film and a BPSG film are sequentially stacked. The BPSG film has a boron concentration in a range from 4.5 mol % to 8.0 mol %. The BPSG film has a phosphorus concentration in a range from 1.0 mol % to 3.5 mol %. The NSG film has a thickness in a range from 50 nm to 400 nm. The BPSG film has a thickness in a range from 400 nm to 800 nm. A distance from the gate insulating film to the BPSG film is at most 100 nm at a portion where the gate insulating film and the BPSG film oppose each other across the NSG film.

Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.

Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.

Abstract: In forming an n+-type source region in a surface region of a p-type base layer by ion implantation, ion implantation of arsenic and ion implantation of nitrogen are sequentially performed. The ion implantation of nitrogen is performed by acceleration energy higher than that of the ion implantation of arsenic. The n+-type source region has an arsenic concentration profile and a nitrogen concentration profile formed to overlap each other at a different depth from the front surface of the base substrate. A peak of the nitrogen concentration profile is positioned deeper than a peak of the arsenic concentration profile from the front surface of the base substrate. The overall impurity concentration distribution of the n+-type source region is a concentration profile that is formed by summing the arsenic concentration profile and the nitrogen concentration profile with each other and whose diffusion depth is large.

Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a first silicon carbide layer of a first conductivity type on a front surface of a silicon carbide semiconductor substrate. A thermal oxidation film is formed on a surface of a base body including the first silicon carbide layer. The thermal oxidation film is subsequently removed using a solution containing hydrofluoric acid. The base body is washed with a mixture of ammonia water and a hydrogen peroxide solution, a mixture of hydrochloric acid and a hydrogen peroxide solution, and a dilute hydrofluoric acid. The base body is held at temperature of 700 degrees C. to 1700 degrees C., and an insulating film is deposited on the base body.

Abstract: A silicon carbide semiconductor device includes: a drift region of a first conductivity type; a base region of a second conductivity type disposed on the drift region; a main electrode contact region of the first conductivity type selectively embedded in a top of the base region at a higher impurity density than the drift region; a trench having a round part on a top surface side of the main electrode contact region to a level that is shallower than a depth of the main electrode contact region, the trench going from the round part through the base region and having a bottom that reaches the drift region; and an insulated gate structure provided on an inner side of the trench. A smallest radius of curvature of the round part is greater than a relatively high impurity region of the main electrode contact region.

Abstract: A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.

Abstract: A gate trench of a MOS gate formed in the front surface of a silicon carbide substrate includes a first portion that includes the bottom surface of the gate trench, a second portion that is connected to the substrate front surface side of the first portion, and a third portion that is connected to the substrate front surface side of the second portion. In the third portion of the gate trench, an n+ source region is exposed along the sidewalls. The width of the third portion of the gate trench is greater than the widths of the first and second portions and of the gate trench. Upper corners of the gate trench smoothly connect the sidewalls to the substrate front surface. The thickness of a gate insulating film smoothly connected along the bottom surface and sidewalls of the gate trench is substantially uniform over the entire inner wall surface of the gate trench.

Abstract: A semiconductor device includes an n-type silicon carbide epitaxial layer on a front surface of an n+-type silicon carbide substrate. A first p+-type base region is provided in the n-type silicon carbide epitaxial layer and a breakdown voltage structure region is provided in an outer periphery of an active region through which a main current flows. A distance between the first p+-type base region and a front surface of the n+-type silicon carbide substrate is smaller than a distance between the breakdown voltage structure region and the front surface of the n+-type silicon carbide substrate.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first silicon carbide layer of the first conductivity type, and an insulating film. In the silicon carbide semiconductor device, no fluorine or chlorine is detectable in the insulating film, at a boundary layer of the insulating film and the first silicon carbide layer, or at the surface of first silicon carbide layer where the insulating film is provided.

Abstract: An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes. Next, the interlayer insulating film and regions exposed by the contact holes are covered by a titanium nitride film, and the titanium nitride film is etched to remain only at portions of the gate insulating film and the interlayer insulating film exposed in the contact holes. The interlayer insulating film and the regions exposed by the contact holes are covered by a nickel film, and after the nickel film directly contacting the interlayer insulating film is removed, the nickel film is heat treated and a nickel silicide layer is formed.

Abstract: A trench gate structure vertical MOSFET includes a silicon carbide substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, a trench, a gate electrode, an interlayer insulating film, a barrier layer, a contact electrode, a first electrode, and a second electrode. The barrier layer includes a layer made of TiN, and the thickness of the TiN layer is 10 to 80 nm. The interlayer insulating film is a laminate film of non-doped silicate glass and borophosphosilicate glass.

Abstract: An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes. Next, the interlayer insulating film and regions exposed by the contact holes are covered by a titanium nitride film, and the titanium nitride film is etched to remain only at portions of the gate insulating film and the interlayer insulating film exposed in the contact holes. The interlayer insulating film and the regions exposed by the contact holes are covered by a nickel film, and after the nickel film directly contacting the interlayer insulating film is removed, the nickel film is heat treated and a nickel silicide layer is formed.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate; a nickel silicide film provided on a surface of the silicon carbide semiconductor substrate and functioning as an ohmic contact; and an extraction electrode contacting the ohmic contact on a side different from a silicon carbide semiconductor substrate side. The silicon carbide semiconductor substrate side of the ohmic contact is mainly formed from a NiSi phase and an extraction electrode side thereof is mainly formed from a Ni2Si phase. The ohmic contact includes carbon on the silicon carbide semiconductor substrate and includes no carbon on the extraction electrode side.

Abstract: A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region contains arsenic.

Abstract: In forming an n+-type source region in a surface region of a p-type base layer by ion implantation, ion implantation of arsenic and ion implantation of nitrogen are sequentially performed. The ion implantation of nitrogen is performed by acceleration energy higher than that of the ion implantation of arsenic. The n+-type source region has an arsenic concentration profile and a nitrogen concentration profile formed to overlap each other at a different depth from the front surface of the base substrate. A peak of the nitrogen concentration profile is positioned deeper than a peak of the arsenic concentration profile from the front surface of the base substrate. The overall impurity concentration distribution of the n+-type source region is a concentration profile that is formed by summing the arsenic concentration profile and the nitrogen concentration profile with each other and whose diffusion depth is large.