Patents by Inventor Makoto Yabuuchi

Makoto Yabuuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210142849
    Abstract: Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.
    Type: Application
    Filed: November 11, 2020
    Publication date: May 13, 2021
    Inventor: Makoto YABUUCHI
  • Patent number: 10971219
    Abstract: A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 6, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10937475
    Abstract: A TCAM (Ternary Content Addressable Memory) according to the embodiment includes repeaters in a delay path for controlling the timing in the replica circuit that defines the timing of matching. According to the above configuration, the TCAM which consumes low power and operates at high speed can be realized.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: March 2, 2021
    Assignee: RENESAS ELELCTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10910056
    Abstract: A semiconductor device includes a plural search memory cells, a plural match lines, a plural sub-ground lines, and a plural amplifiers. The search memory cells are disposed in a matrix form. The match lines are disposed in association with respective memory cell rows and used to determine whether search data matches data stored in the search memory cells. The sub-ground lines are disposed in association with respective memory cell rows. The amplifiers are disposed in association with respective memory cell rows to amplify the potentials of the match lines. The match lines and the sub-ground lines are respectively precharged to a first potential and a second potential before a data search. When the search data is mismatched, the match lines are electrically coupled to associated sub-ground lines through the search memory cells and set to an intermediate potential that is intermediate between the first potential and the second potential.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: February 2, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10825814
    Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: November 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Yuichiro Ishii
  • Publication number: 20200342936
    Abstract: A semiconductor device includes a first wiring having a first portion, a second portion, a third portion provided between the first portion and the second portion, memory cells connected to the third portion of the first wiring, a field effect transistor having a drain connected to the second portion, and a gate, and a second wiring provided in parallel with the first wiring. The third portion of the first wiring includes a fourth portion located nearest to the first portion and a fifth portion located nearest to the second portion. The first wiring further includes a sixth portion disposed between the first portion and the fourth portion. The memory cells include a first memory cell connected to the fourth portion and a second memory cell connected to the fifth portion. The second wiring is electrically connected between the sixth portion and the gate of the field effect transistor.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 29, 2020
    Inventors: Yoshisato YOKOYAMA, Makoto YABUUCHI
  • Patent number: 10811405
    Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 20, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama
  • Publication number: 20200257501
    Abstract: A semiconductor device that can reduce power consumption while improving the accuracy of learning and inference is provided. The semiconductor device is connected to data lines PBL, NBL, and comprises a product operation memory cell 1 for storing data of ternary value and performing a product-sum operation between a stored data and an input data INP and a data in the data lines PBL, NBL.
    Type: Application
    Filed: February 5, 2020
    Publication date: August 13, 2020
    Inventor: Makoto YABUUCHI
  • Patent number: 10734374
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: August 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
  • Patent number: 10705143
    Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Patent number: 10706917
    Abstract: Provided is a semiconductor memory device having a low power consumption write assist circuit. The semiconductor memory device includes multiple word lines, multiple bit line pairs, multiple memory cells, multiple auxiliary line pairs, a write driver circuit, a write assist circuit, and a select circuit. The memory cells are coupled to the word lines and the bit line pairs in such a manner that one memory cell is coupled to one word line and one bit line pair. The auxiliary line pairs run parallel to the bit line pairs in such a manner that one auxiliary line pair runs parallel to one bit line pair. The select circuit couples, to the write driver circuit, one bit line pair selected from the bit line pairs in accordance with a select signal, and couples, to the write assist circuit, an associated auxiliary line pair running parallel to the selected bit line pair.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Yuichiro Ishii, Yohei Sawada, Makoto Yabuuchi
  • Publication number: 20200202923
    Abstract: A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.
    Type: Application
    Filed: October 30, 2019
    Publication date: June 25, 2020
    Inventors: Makoto YABUUCHI, Shinji TANAKA
  • Patent number: 10672463
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10644009
    Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi
  • Patent number: 10629264
    Abstract: A content addressable memory includes a plurality of TCAM cells which configure one entry, a first word line coupled to the TCAM cells, a second word line coupled to the TCAM cells and a match line coupled to the TCAM cells and further includes a valid cell which stores a valid bit which indicates validity or invalidity of the entry, a bit line coupled to the valid line and a selection circuit which is coupled to the first word line and the second word line and sets the valid cell to a selected state in accordance with a situation where the first word line or the second word line is set to the selected state.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Masao Morimoto
  • Patent number: 10600483
    Abstract: An object of the present disclosure is to provide a content addressable memory realizing higher speed of a search access. A content addressable memory includes: a plurality of memory cells; a match line coupled to the plurality of memory cells; a search line coupled to each of the plurality of memory cells; a match line output circuit coupled to the match line; and a potential changing circuit coupled to the match line and changing the potential of the match line.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 24, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10580484
    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Hidehiro Fujiwara
  • Patent number: 10580490
    Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Koji Nii
  • Patent number: 10566329
    Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10541028
    Abstract: A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi