Patents by Inventor Makoto Yabuuchi

Makoto Yabuuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10705143
    Abstract: An object of the present invention is to provide a highly-reliable content addressable memory. Provided is a content addressable memory including: a plurality of CAM cells; a word line joined to the CAM cells; a plurality of bit lines joined to the CAM cells; a plurality of search lines joined to the CAM cells; a match line joined to the CAM cells; a match amplifier joined to the match line; and a selection circuit that can select the output of the match amplifier in accordance with the value of the word line.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Shinji Tanaka
  • Publication number: 20200202923
    Abstract: A semiconductor device capable of improving operating margins is provided. The semiconductor device comprises a memory circuit including a memory cell comprised of a SOTB transistor, and a mode designation circuit switching operation modes of the memory circuit for a first mode or a second mode. The memory circuit includes a substrate bias generation circuit supplying a substrate bias voltage to the SOTB transistor and a timing signal generation circuit generating a timing signal used for a reading operation or a writing operation of the memory circuit. The substrate bias generation circuit does not supply the substrate bias voltage to the SOTB transistor in the second mode.
    Type: Application
    Filed: October 30, 2019
    Publication date: June 25, 2020
    Inventors: Makoto YABUUCHI, Shinji TANAKA
  • Patent number: 10672463
    Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: June 2, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10644009
    Abstract: To provide a semiconductor memory device fast in address access time. The semiconductor memory device includes a plurality of memory cells, and a word line coupled to the memory cells. The word line is extended in a first direction. Each of the memory cells includes gate electrodes extended in a second direction intersecting with the first direction.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi
  • Patent number: 10629264
    Abstract: A content addressable memory includes a plurality of TCAM cells which configure one entry, a first word line coupled to the TCAM cells, a second word line coupled to the TCAM cells and a match line coupled to the TCAM cells and further includes a valid cell which stores a valid bit which indicates validity or invalidity of the entry, a bit line coupled to the valid line and a selection circuit which is coupled to the first word line and the second word line and sets the valid cell to a selected state in accordance with a situation where the first word line or the second word line is set to the selected state.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: April 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Masao Morimoto
  • Patent number: 10600483
    Abstract: An object of the present disclosure is to provide a content addressable memory realizing higher speed of a search access. A content addressable memory includes: a plurality of memory cells; a match line coupled to the plurality of memory cells; a search line coupled to each of the plurality of memory cells; a match line output circuit coupled to the match line; and a potential changing circuit coupled to the match line and changing the potential of the match line.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 24, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10580490
    Abstract: A semiconductor device is provided where high-speed search operation can be performed. The semiconductor device includes a plurality of search memory cells arranged in a matrix form a plurality of search line pairs which are respectively provided corresponding to memory cell columns and which respectively transmit a plurality of search data to be compared with data stored in the search memory cells, a plurality of search drivers which are respectively arranged at corresponding to one end sides of the search line pairs and which drive the search line pairs according to the search data, and a plurality of assist circuits which are respectively provided corresponding to the other end sides of the search line pairs and which assist driving corresponding search line pairs according to the search data.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Koji Nii
  • Patent number: 10580484
    Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Makoto Yabuuchi, Hidehiro Fujiwara
  • Patent number: 10566329
    Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventor: Makoto Yabuuchi
  • Patent number: 10541028
    Abstract: A semiconductor storage device includes: a first memory cell joined to first and second word lines and a first match line; and a second memory cell joined to the first and second word lines and a second match line. The first and second memory cells are arranged adjacent to each other in planar view, and the first and second word lines are formed using wirings of a first wiring layer. The first and second match lines are formed using wirings of a second wiring layer provided adjacent to the first wiring layer. The first and second word lines are provided in parallel with each other between two first wirings to which a first reference potential is supplied. The first and second match lines are provided in parallel with each other between two second wirings to which the first reference potential is supplied.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: January 21, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10510400
    Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiaki Sano, Ken Shibata, Shinji Tanaka, Makoto Yabuuchi, Noriaki Maeda
  • Patent number: 10510761
    Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: December 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Kengo Masuda
  • Publication number: 20190378831
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 12, 2019
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi OKAGAKI, Koji SHIBUTANI, Makoto YABUUCHI, Nobuhiro TSUDA
  • Patent number: 10490264
    Abstract: The semiconductor device includes a supply circuit for supplying a boosted voltage to a distal end of a wiring driven by a drive signal. The supply circuit includes an inverter circuit having an input coupled to the wiring, and a switch element controlled by an output signal of the inverter circuit. The switch element couples the boosted voltage to the distal end of the wiring.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: November 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinji Tanaka, Makoto Yabuuchi
  • Patent number: 10490545
    Abstract: An area of a semiconductor device having a FINFET can be reduced. The drain regions of an n-channel FINFET and a p-channel FINFET are extracted by two second local interconnects from a second Y gird between a gate electrode and a dummy gate adjacent thereto, to a third Y grid adjacent to the second Y gird. These second local interconnects are connected by a first local interconnect extending in the X direction in the third Y grid. According to such a cell layout, although the number of grids is increased by one because of the arrangement of the first local interconnect, the length in the X direction can be reduced. As a result, the cell area of the unit cell can be reduced while a space between the first and second local interconnects is secured.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Okagaki, Koji Shibutani, Makoto Yabuuchi, Nobuhiro Tsuda
  • Publication number: 20190355712
    Abstract: A semiconductor device includes a semiconductor substrate, a memory cell formed on the semiconductor substrate, a word line connected to the memory cell, and an auxiliary line connected to the word line.
    Type: Application
    Filed: July 31, 2019
    Publication date: November 21, 2019
    Inventors: Yuta YOSHIDA, Makoto YABUUCHI, Yoshisato YOKOYAMA
  • Patent number: 10475521
    Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 12, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Makoto Yabuuchi
  • Patent number: 10460795
    Abstract: A semiconductor device includes a latch circuit receiving a first signal, generated in synchronization with a clock signal, from a pulse generation circuit, and generating a second signal; a first delay circuit receiving the second signal from the latch circuit, and generating a third signal by delaying the second signal; a second delay circuit receiving the third signal from the first delay circuit, and generating a fourth signal by delaying the third signal; and a logic circuit receiving the second and fourth signals from the latch and second delay circuits, respectively, and generating a word line control signal based on one of the second signal and the fourth signal. The latch circuit generates the second signal of a first level based on the first signal, and generates the second signal of a second level, which is different from the first level, based on the third signal.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichiro Ishii, Makoto Yabuuchi, Masao Morimoto
  • Patent number: 10453519
    Abstract: A semiconductor device includes a SRAM (Static Random Access Memory) circuit. The SRAM circuit includes a static memory cell, a word line coupled with the static memory cell, a pair of bit lines coupled with the static memory cell, a first interconnection coupled with the static memory cell, and supplying a first potential, a second interconnection coupled with the static memory cell, and supplying a second potential lower than the first potential, a first potential control circuit controlling a potential of the second interconnection, and a second potential control circuit controlling a potential of the first interconnection. The SRAM circuit includes, as an operation mode a first operation mode for reading data from the SRAM circuit, or for writing data into the SRAM circuit, and a second operation mode for reducing power consumption than the first operation mode.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: October 22, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yohei Sawada, Makoto Yabuuchi, Yuichiro Ishii
  • Patent number: 10424575
    Abstract: Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of a FINFET, an auxiliary line AL is arranged in the space created in the third wiring layer, and this auxiliary line AL and a word line WL are electrically connected to each other. Thus, a measure (device) based on such new knowledge that rising time of a word line voltage is largely affected by a wiring resistance of the word line is achieved, a high-speed operation in an SRAM using the FINFET is achieved.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: September 24, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuta Yoshida, Makoto Yabuuchi, Yoshisato Yokoyama