Patents by Inventor Mamoru Sasaki

Mamoru Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190178693
    Abstract: A thermal mass flow sensor 10 enclosed airtightly in a sealed container 11 under an inert atmosphere for the purpose of suppressing disappearance of a coating layer on sensor wires 13a and 13b in association with use at a high temperature, further comprises an air release pipe 16 that is a pipe which brings an internal space and outside of the sealed container 11 in airtight communication with each other through an air release hole 16a that is a through-hole formed in an outer wall of the sealed container 11. An end of the air release pipe 16 on an opposite side to the air release hole 16a is sealed by plastic deformation to form a sealed part 16b. Thereby, after forming the sealed container 11 under a normal atmosphere, the internal space of the sealed container 11 can be closed airtightly. The sealed part 16b may be further sealed by welding.
    Type: Application
    Filed: February 17, 2017
    Publication date: June 13, 2019
    Inventors: Ryu Sasaki, Mamoru Ishii
  • Patent number: 8844858
    Abstract: A wire winding device which uses a large-sized supply bobbin, which has a large capacity and a large diameter, to highly precisely suppress a variation in tension which variation occurs when a coil is formed by winding a wire material at high speed with the wire material aligned with a winding frame. Rotation (the number of rotation, and timing) of the supply bobbin relative to rotation of the coil is controlled based on the difference between the amount of take-up of the wire material taken up on the winding frame side and the amount of pay-out of the wire material paid out from the supply bobbin, and the control is performed such that the amount of the take-up and the amount of the pay-out agree with each other every moment. This can highly precisely suppress a variation in tension even if there are large differences between inertia of and the diameters of the coil and the supply bobbin.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: September 30, 2014
    Assignee: Honda Motor Co., Ltd.
    Inventors: Koichi Kimura, Takuro Kugimiya, Masahito Kakema, Mamoru Sasaki, Junko Tanaka
  • Patent number: 8476801
    Abstract: An apparatus for manufacturing a stator. On a split core of the stator, there are wound main conductors and two auxiliary conductors, which are thinner than but correspond to the main conductors. These main conductors are arrayed and wound in a plurality of layers, such that the main conductors of an upper layer are arranged in the valleys between the adjoining main conductors of a layer. For the main conductors of a first layer, the auxiliary conductors are arranged in a first space and a second space. For the main conductors of the second and subsequent layers, the auxiliary conductors are arranged in a third space, and the auxiliary conductors are arranged in a fourth space.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: July 2, 2013
    Assignee: Honda Motor Co., Ltd.
    Inventors: Hitoshi Shiobara, Mamoru Sasaki, Kenji Misao, Mitsuhiro Yamada
  • Patent number: 7974648
    Abstract: A transmitter (1) applies current from a power supply node to a ground node in synchronization with only a rise of an input signal and transmits a transmission signal including an RF pulse signal to a receiver (2). The receiver (2) applies current from a node (231) on which precharge is performed to a ground node only at the reception of the RF pulse signal, decreases the potential of the node (231) from a precharge potential Va to 0 V, and outputs an H-level output signal by detecting the decreased potential 0 V. After receiving the RF pulse signal, the receiver (2) performs precharge to change the potential of the node (231) to the potential Va.
    Type: Grant
    Filed: June 13, 2008
    Date of Patent: July 5, 2011
    Assignee: Hiroshima University
    Inventor: Mamoru Sasaki
  • Publication number: 20110114781
    Abstract: A wire winding device which uses a large-sized supply bobbin, which has a large capacity and a large diameter, to highly precisely suppress a variation in tension which variation occurs when a coil is formed by winding a wire material at high speed with the wire material aligned with a winding frame. Rotation (the number of rotation, and timing) of the supply bobbin relative to rotation of the coil is controlled based on the difference between the amount of take-up of the wire material taken up on the winding frame side and the amount of pay-out of the wire material paid out from the supply bobbin, and the control is performed such that the amount of the take-up and the amount of the pay-out agree with each other every moment. This can highly precisely suppress a variation in tension even if there are large differences between inertia of and the diameters of the coil and the supply bobbin.
    Type: Application
    Filed: June 1, 2009
    Publication date: May 19, 2011
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Koichi Kimura, Takuro Kugimiya, Masahito Kakema, Mamoru Sasaki, Junko Tanaka
  • Publication number: 20110025163
    Abstract: An apparatus for manufacturing a stator. On a split core of the stator, there are wound main conductors and two auxiliary conductors, which are thinner than but correspond to the main conductors. These main conductors are arrayed and wound in a plurality of layers, such that the main conductors of an upper layer are arranged in the valleys between the adjoining main conductors of a layer. For the main conductors of a first layer, the auxiliary conductors are arranged in a first space and a second space. For the main conductors of the second and subsequent layers, the auxiliary conductors are arranged in a third space, and the auxiliary conductors are arranged in a fourth space.
    Type: Application
    Filed: March 16, 2009
    Publication date: February 3, 2011
    Applicant: HONDA MOTOR CO., LTD.
    Inventors: Hitoshi Shiobara, Mamoru Sasaki, Kenji Misao, Mitsuhiro Yamada
  • Publication number: 20100216395
    Abstract: A transmitter (1) applies current from a power supply node to a ground node in synchronization with only a rise of an input signal and transmits a transmission signal including an RF pulse signal to a receiver (2). The receiver (2) applies current from a node (231) on which precharge is performed to a ground node only at the reception of the RF pulse signal, decreases the potential of the node (231) from a precharge potential Va to 0 V, and outputs an H-level output signal by detecting the decreased potential 0 V. After receiving the RF pulse signal, the receiver (2) performs precharge to change the potential of the node (231) to the potential Va.
    Type: Application
    Filed: June 13, 2008
    Publication date: August 26, 2010
    Inventor: Mamoru Sasaki
  • Patent number: 7545663
    Abstract: Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.
    Type: Grant
    Filed: May 25, 2006
    Date of Patent: June 9, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Mamoru Sasaki, Atsushi Iwata
  • Patent number: 7538603
    Abstract: Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends of the differential signal transmission line are connected via an inductor, a low-amplitude segment is eliminated by a phase shift in the inductor and a standing wave of substantially uniform phase and amplitude is produced, wherein the number of lines connected to the grid point is made the same for entire grid points.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: May 26, 2009
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Mamoru Sasaki, Atsushi Iwata, Mitsuru Shiozaki, Atsushi Mori
  • Patent number: 7336123
    Abstract: In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.
    Type: Grant
    Filed: March 28, 2006
    Date of Patent: February 26, 2008
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Takayuki Mashimo, Yoshihiro Masui, Junji Nakatsuka
  • Publication number: 20070285179
    Abstract: Provided is a grid-type high-speed clock signal distribution network capable of reducing a difference in amplitude of a standing wave on a transmission line and of supplying a signal from any position. The network for transmitting the clock signal is such that ends of the differential signal transmission line are connected via an inductor, a low-amplitude segment is eliminated by a phase shift in the inductor and a standing wave of substantially uniform phase and amplitude is produced, wherein the number of lines connected to the grid point is made the same for entire grid points.
    Type: Application
    Filed: May 4, 2007
    Publication date: December 13, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Hiroaki Ikeda, Mamoru Sasaki, Atsushi Iwata, Mitsuru Shiozaki, Atsushi Mori
  • Patent number: 7301399
    Abstract: In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current Io, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current Io, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: November 27, 2007
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Kunihiko Gotoh
  • Publication number: 20070005876
    Abstract: Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.
    Type: Application
    Filed: May 25, 2006
    Publication date: January 4, 2007
    Inventors: Hiroaki Ikeda, Mamoru Sasaki, Atsushi Iwata
  • Publication number: 20060244521
    Abstract: In a chopper amplifier circuit operable at a low voltage utilizing a switched operational amplifier, a chopper modulator chopper-modulates an input signal according to a predetermined control signal, and outputs a chopper-modulated signal. An amplifier circuit constituted by the switched operational amplifier amplifies the chopper-modulated signal outputted from the chopper modulator, and outputs an amplified chopper-modulated signal. A chopper-demodulator of the switched operational amplifier chopper-demodulates the amplified chopper-modulated signal outputted from the amplifier circuit according to the control signal, and outputs a demodulated output signal as a chopper-amplified output signal from an output terminal. A chopper modulator chopper-modulates a demodulated signal outputted from the chopper demodulator according to the control signal, and outputs a chopper-modulated signal to an input terminal of the amplifier circuit.
    Type: Application
    Filed: March 28, 2006
    Publication date: November 2, 2006
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Takayuki Mashimo, Yoshihiro Masui, Junji Nakatsuka
  • Patent number: 7098682
    Abstract: The invention relates to a test method and a test apparatus for a semiconductor integrated circuit device having a high-speed input/output device, and it has for its object to perform the test of the high-speed I/O exceeding 1 GHz, promptly by a simple board construction, without altering a test system for individual I/O specifications. A semiconductor integrated circuit device (1) having a high-speed input/output device (2) is set on a load board (3) which is provided with loopback paths (4) each connecting the external output terminal and external input terminal of the semiconductor integrated circuit device (1) by transmission lines, and the operation of the high-speed input/output device (2) is tested within the semiconductor integrated circuit device (1) by utilizing test means (5) disposed inside the semiconductor integrated circuit device (1), and the loopback paths (4).
    Type: Grant
    Filed: December 3, 2002
    Date of Patent: August 29, 2006
    Assignee: Japan Science and Technology Agency
    Inventor: Mamoru Sasaki
  • Publication number: 20060114061
    Abstract: In a class AB CMOS output circuit provided with a CMOS circuit including first P and N channel transistors and operating by a predetermined operating current Io, a replica circuit is formed on a semiconductor substrate of the CMOS circuit, and includes a second P channel transistor having a size equal or similar to that of the first P channel transistor, and a second N channel transistor having a size equal or similar to that of the first N channel transistor. A bias voltage supply allows the second P and N channel transistors to operate based on a reference current Iref corresponding to the operating current Io, applies a first bias voltage as applied to the second P channel transistor to the first P channel transistor, and applies a second bias voltage as applied to the second N channel transistor to the first N channel transistor.
    Type: Application
    Filed: November 28, 2005
    Publication date: June 1, 2006
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Kunihiko Gotoh
  • Patent number: 7015841
    Abstract: In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.
    Type: Grant
    Filed: January 6, 2005
    Date of Patent: March 21, 2006
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Miho Akagi, Kunihiko Goto
  • Publication number: 20050200510
    Abstract: In a sampling and holding, a control logic circuit connects another end of each capacitor of a DA converter to a ground potential, and outputs a sampled input analog signal from a switched amplifier to one end of a hold capacitor to hold. In a successive approximation, it controls a switched amplifier to set an output terminal thereof to a high-impedance state and the hold capacitor to connect the one end thereof to the ground potential. Then, it switches over connection of another end of each capacitor from the ground potential to a power supply voltage based on a digital value held by a successive approximation register to output an output voltage from another end of the hold capacitor to a comparator, and compares the output voltage from another end thereof with an intermediate reference voltage to obtain a digital value from the successive approximation register.
    Type: Application
    Filed: January 6, 2005
    Publication date: September 15, 2005
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Takeshi Yoshida, Atsushi Iwata, Mamoru Sasaki, Miho Akagi, Kunihiko Goto
  • Publication number: 20050077905
    Abstract: The invention relates to a test method and a test apparatus for a semiconductor integrated circuit device having a high-speed input/output device, and it has for its object to perform the test of the high-speed I/O exceeding 1 GHz, promptly by a simple board construction, without altering a test system for individual I/O specifications. A semiconductor integrated circuit device (1) having a high-speed input/output device (2) is set on a load board (3) which is provided with loopback paths (4) each connecting the external output terminal and external input terminal of the semiconductor integrated circuit device (1) by transmission lines, and the operation of the high-speed input/output device (2) is tested within the semiconductor integrated circuit device (1) by utilizing test means (5) disposed inside the semiconductor integrated circuit device (1), and the loopback paths (4).
    Type: Application
    Filed: December 3, 2002
    Publication date: April 14, 2005
    Inventor: Mamoru Sasaki
  • Patent number: 6340546
    Abstract: Positive photosensitive resin compositions, which comprise (A) a polyamidate having repetitive units of general formula (I) wherein R1 is a tetravalent organic group, R2 is a divalent organic group having a phenolic hydroxyl group, three R3 groups and three R4 groups each independently are an alkyl group or a hydrogen atom, and at least two R3 groups and at least two R4 groups are alkyl groups, and (B) a compound capable of generating an acid when exposed to light, are improved in storage stability and exposure sensitivity to i-line. Such compositions can improve the reliability of electronic parts when formed into surface-protecting films or interlayer insulating films by a method including exposure to i-line, development and heating.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: January 22, 2002
    Assignees: Hitachi Chemical Dupont Microsystems Ltd., Hitachi Chemical Dupont Microsystems L.L.C.
    Inventor: Mamoru Sasaki