Patents by Inventor Mamoru Sekiya

Mamoru Sekiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9787319
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 10, 2017
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Patent number: 9590654
    Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
    Type: Grant
    Filed: January 12, 2015
    Date of Patent: March 7, 2017
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Publication number: 20160241256
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtractor, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Application
    Filed: April 25, 2016
    Publication date: August 18, 2016
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA
  • Patent number: 9350378
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: May 24, 2016
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Patent number: 9287867
    Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: March 15, 2016
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Patent number: 9240783
    Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: January 19, 2016
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Tsuyoshi Kawaguchi, Mamoru Sekiya
  • Publication number: 20150207519
    Abstract: Provided is a circuit which can correct an output state in real time and reduce influences of distortion/noise components generated by a delay device. A signal modulation circuit includes a subtractor, an integrator, a phase inverting circuit, a DFF for while inserting a zero level at timing synchronous with the clock signal, delaying and quantizing the signal, a ternary signal generating circuit for generating a ternary signal for selectively driving a load connected to a single power supply into ternary conductive states including a positive current on-state, a negative current on-state, and an off-state, a driver circuit for generating a driving signal for driving a load, and a feedback circuit for feeding back the driving signal from the driver circuit to the input signal.
    Type: Application
    Filed: January 12, 2015
    Publication date: July 23, 2015
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA
  • Patent number: 8970269
    Abstract: A pulse width modulation signal with a less distortion component that is not influenced by a common-mode noise or an offset voltage is generated. Pulse signal generation circuits 6, 7 generate pulse signals S1, S2 whose pulse widths are discharge times t1, t2 of integrators 3, 4, respectively, a PWM signal generation circuit 8 detects discharge end timings of the integrators 3, 4 based on the pulse signals S1, S2, and a pulse whose pulse width is a time between discharge end timing of one of the integrators 4 and discharge end timing of the other one of the integrators 3 is generated so as to be output as a PWM signal Spwm.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: March 3, 2015
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Mamoru Sekiya
  • Publication number: 20140363032
    Abstract: Provided is a modulation circuit that can correct an output state in real time and reliably modulate an input signal to output the modulated signal. The signal modulation circuit includes a subtracter, an integrator, a chopper circuit, a frequency divider, and a D-type flip-flop. A delay circuit of a sigma delta modulation circuit is not provided to a feedback circuit, and a signal is delayed and quantized in the D-type flip-flop. The chopper circuit inserts a zero level at timing synchronized with a clock signal, so that pulse density modulation is performed.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA
  • Publication number: 20140361809
    Abstract: A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.
    Type: Application
    Filed: June 4, 2014
    Publication date: December 11, 2014
    Inventors: Yoshinori NAKANISHI, Tsuyoshi KAWAGUCHI, Mamoru SEKIYA
  • Publication number: 20140185836
    Abstract: A pulse width modulation signal with a less distortion component that is not influenced by a common-mode noise or an offset voltage is generated. Pulse signal generation circuits 6, 7 generate pulse signals S1, S2 whose pulse widths are discharge times t1, t2 of integrators 3, 4, respectively, a PWM signal generation circuit 8 detects discharge end timings of the integrators 3, 4 based on the pulse signals S1, S2, and a pulse whose pulse width is a time between discharge end timing of one of the integrators 4 and discharge end timing of the other one of the integrators 3 is generated so as to be output as a PWM signal Spwm.
    Type: Application
    Filed: December 18, 2013
    Publication date: July 3, 2014
    Applicant: Onkyo Corporation
    Inventors: Yoshinori NAKANISHI, Mamoru SEKIYA
  • Patent number: 8570083
    Abstract: A pulse width modulation circuit of the present invention changes a voltage of a charging circuit based on an input signal voltage and in synchronization with a first switching signal; changes, during a predetermined second period following a first period during which the voltage of the charging unit is changed, the voltage of the charging unit in an opposite direction to a direction in which the voltage is changed during the first period, based on a constant bias current; detects time starting from when the second period starts to when the voltage of the charging unit reaches a predetermined reference voltage; and generates, based on the detected time which is repeatedly output each time the first switching signal is output, a pulse signal having a pulse width of the time.
    Type: Grant
    Filed: August 22, 2008
    Date of Patent: October 29, 2013
    Assignee: Onkyo Corporation
    Inventors: Yoshinori Nakanishi, Mamoru Sekiya
  • Patent number: 8552802
    Abstract: An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided to an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: October 8, 2013
    Assignee: Onkyo Corporation
    Inventors: Tsuyoshi Kawaguchi, Norimasa Kitagawa, Mamoru Sekiya, Naofumi Shimasaki, Yu Takehara
  • Patent number: 8310307
    Abstract: The first emitter follower circuit and the second emitter follower circuit can increase an input impedance on the side of the inverting input terminal in the amplifying circuit. As a result, when a feedback circuit is connected between the inverting input terminal and the output terminal of the amplifying circuit, a fluctuation in a gain of the amplifying circuit according to a configuration of the feedback circuit can be suppressed.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: November 13, 2012
    Assignee: Onkyo Corporation
    Inventors: Tsuyoshi Kawaguchi, Mamoru Sekiya, Yu Takehara, Norimasa Kitagawa
  • Publication number: 20120049895
    Abstract: An amplifying circuit comprises: a first transistor, a second transistor, a third transistor and a fourth transistor provided to an input stage; and a first bias circuit. The input signal is input into a control terminal of the first transistor and a control terminal of the second transistor, a first terminal of the first transistor is connected to a first terminal of the third transistor, a first terminal of the second transistor is connected to a first terminal of the fourth transistor, a second terminal of the first transistor is connected to a first potential, a second terminal of the second transistor is connected to a second potential that is equal to or different from the first potential, a second terminal of the third transistor is connected to a third potential, a second terminal of the fourth transistor is connected to a fourth potential, the first bias circuit is connected between a control terminal of the third transistor and a control terminal of the fourth transistor.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 1, 2012
    Applicant: ONKYO CORPORATION
    Inventors: Tsuyoshi KAWAGUCHI, Norimasa KITAGAWA, Mamoru SEKIYA, Naofumi SHIMASAKI, Yu TAKEHARA
  • Publication number: 20120049963
    Abstract: The first emitter follower circuit and the second emitter follower circuit can increase an input impedance on the side of the inverting input terminal in the amplifying circuit. As a result, when a feedback circuit is connected between the inverting input terminal and the output terminal of the amplifying circuit, a fluctuation in a gain of the amplifying circuit according to a configuration of the feedback circuit can be suppressed.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 1, 2012
    Applicant: ONKYO CORPORATION
    Inventors: Tsuyoshi KAWAGUCHI, Mamoru SEKIYA, Yu TAKEHARA, Norimasa KITAGAWA
  • Patent number: 7835538
    Abstract: The loudspeaker includes a dome diaphragm that is made of a base material impregnated in a thermosetting resin; a cone diaphragm whose outer circumference side end portion is coupled with an outer circumference end portion of the dome diaphragm; and a voice coil having a bobbin whose one end is coupled to a back surface of the dome diaphragm, and whose outer curved surface is coupled with an inner circumference end portion of the cone diaphragm, wherein the dome diaphragm is provided with a plurality of cone-shaped projections that is formed by hardening the thermosetting resin, projecting from the back surface, and disposed in a circular pattern with a space between each other, the plurality of cone-shaped projections defining a coupling portion to which the one end of the bobbin is coupled.
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: November 16, 2010
    Assignee: Onkyo Corporation
    Inventors: Takeru Inoue, Mamoru Sekiya
  • Patent number: 7773373
    Abstract: The present invention provides a vibration-damping structure for an audio apparatus, accommodating a main transformer, which becomes a vibration source when driven, the vibration-damping structure including: a main chassis to which a signal processing board for processing an audio signal is attached, the first chassis defining a portion of an outer shape of an assembly of the vibration-damping structure; a sub-chassis fastened to an inner surface of the main chassis so as to be partially in contact with the inner surface of the main chassis via a plurality of fastening members; and a component accommodating chassis fastened to an inner surface of the sub-chassis so as to be partially in contact with the inner surface of the sub-chassis via other fastening members, wherein the main transformer is fixed to the component accommodating chassis.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: August 10, 2010
    Assignee: Onkyo Corporation
    Inventors: Tsuyoshi Morohashi, Mamoru Sekiya, Norio Etoh, Norimasa Kitagawa
  • Patent number: 7710175
    Abstract: A pulse width modulation circuit includes a first electric-charge accumulator; a second electric-charge accumulator; a first current generator which generates a first current corresponding to the amplitude of an input AC voltage; a second current generator which generates a second current with a constant value; a first current supply controller which supplies the first current to the first electric-charge accumulator; a second current supply controller which supplies the second current to the first electric-charge accumulator; a third current supply controller which supplies the first current to the second electric-charge accumulator; a fourth current supply controller which supplies the second current to the second electric-charge accumulator; and a current limiter which limits the first current to a third current with a predetermined current value, if the amplitude of the AC voltage in the negative side exceeds a predetermined level.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: May 4, 2010
    Assignee: ONKYO Corporation
    Inventors: Yoshinori Nakanishi, Mamoru Sekiya
  • Patent number: 7652358
    Abstract: A semiconductor device according to a preferred embodiment of the present invention is a semiconductor device including a main substrate and one or more sub substrates, and the semiconductor device includes first heat generating devices mounted on the sub substrates, sub-substrate heatsinks mounted to the first heat generating devices, and a main-substrate heatsink mounted to the main substrate, wherein the sub-substrate heatsinks and the main-substrate heatsink are secured to each other, such that there is a predetermined positional relationship between the sub substrates and the main substrate.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: January 26, 2010
    Assignee: Onkyo Corporation
    Inventors: Atsushi Minakawa, Mamoru Sekiya, Norio Umezu