Patent number: 6216236
Abstract: A computer system has a plurality of processing units (2-1,2-2,2-n) connected via one or more system buses (1-1,1-2). Each processing unit (2-1,2-2,2-n) has three or more processors (20-1,20-2,20-3) on a common support board (PL) and controlled by a common clock unit (1000). The three processors (20-1,20-2,20-3) perform the same operation and a fault in a processor (20-1,20-2, 20-3) is detected by comparison of the operations of the three processors (20-1,20-2,20-3). If one processor (20-1,20-2,20-3) fails, the operation can continue in the other two processors (20-1,20-2,20-3) of the processing unit (2-1,2-2,2-n), at least temporarily, before replacement of the entire processing unit (2-1,2-2, 2-n). Furthermore, the processing unit (2-1,2-2,2-n) may have a plurality of clocks (A,B) within the clock unit (1000), with a switching arrangement so that the processors (20-1,20-2,20-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails.
Type:
Grant
Filed:
November 10, 1998
Date of Patent:
April 10, 2001
Assignees:
Tokyo, Japan, Hitachi Process Computer Engineering, Inc.
Inventors:
Takeshi Miyao, Manabu Araoka, Tomoaki Nakamura, Masayuki Tanji, Shigenori Kaneko, Koji Masui, Saburou Iijima, Nobuyasu Kanekawa, Shinichiro Kanekawa, Yoshiki Kobayashi, Hiroaki Fukumaru, Katsunori Tagiri