Abstract: An interposer is provided that suppresses heat conduction more effectively between two heat sources when the interposer is placed between the heat sources. An interposer 24 comprises a body having a cavity 23 maintained in vacuum; insulating layers 22a and 22b formed respectively on upper and lower walls 20a and 20b of the body; and heat reflecting layers 21a and 21b formed respectively on the insulating layers 22a and 22b. The interposer 24 thermally insulates semiconductor devices 11a and 21a mounted respectively on upper and lower sides of the interposer 24.

Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.

Abstract: A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.

Abstract: A method of forming a low-resistance, high-reliability through/embedded electrode is provided, where the electrode can be arranged in a higher density according to the miniaturization of the semiconductor manufacturing technology. This method includes the step of filling an opening 51 of a substrate 50 with a paste 56 of a first conductive material and drying the paste 56; the step of solid-phase sintering the paste 56 filled in the opening 51, generating a first porous conductor 57; the step of applying a paste of a second conductive material so as to cover the first conductor 57; and the step of melting the paste of the second conductive material by heat treatment, impregnating the second conductive material into the first conductor 57.

Abstract: To provide a mounting structure of a semiconductor device/electronic component that suppresses temperature rise of a semiconductor device and/or an electronic component having large power consumption due to heat generation thereof, resulting in stable operation. The mounting comprises an interposer 10; a semiconductor device 11 mounted on the surface 10a of the interposer 10; and a cover 12 that forms an inner space S along with the interposer 10; wherein the cover 12 is closely adhered and fixed on the surface 10a of the interposer 10 to so as to include the semiconductor device 11. The cover 12 has an inlet 13 for introducing a heat-absorbing fluid L from outside, and an outlet 14 for discharging the fluid L from the inner space S to outside. The inner space S is a closed space excluding the inlet 13 and the outlet 14.

Abstract: An interposer is provided that suppresses heat conduction more effectively between two heat sources when the interposer is placed between the heat sources. An interposer 24 comprises a body having a cavity 23 maintained in vacuum; insulating layers 22a and 22b formed respectively on upper and lower walls 20a and 20b of the body; and heat reflecting layers 21a and 21b formed respectively on the insulating layers 22a and 22b. The interposer 24 thermally insulates semiconductor devices 11a and 21a mounted respectively on upper and lower sides of the interposer 24.

Abstract: [Aim of Invention] Providing the effective semiconductor miniaturization and its higher-dense fine wiring with the through-hole and the buried via electrode structure of the lower resistivity and higher reliability material at the low cost manufacturing method. [Solution] Preparing the sedimentation layer 57 buried at first the dried-sintered-porous metal material of paste 56 in the through-hole 51 having a insulation layer 54 on the board structure 50, fully covered over the porous area top of the sedimentation layer 57 with the second metal paste and then full-filling the second metal into the porous area of the sedimentation layer 57.

Abstract: Image quality degradation due to external light irradiated to an edge section of a transparent cover of a solid-state imaging device and external light propagating in the cover is prevented with a simple structure. A glass cover 60 formed to cover the whole surface of an imaging region 26 of a solid-state imaging element 10 is constituted by a transmission section 60a corresponding to the imaging region 26, and an edge section 60b that surrounds the transmission section 60a outside the transmission section 60a. The edge section 60b of the cover 60 is selectively removed around a periphery of the edge section 60b, thereby forming a frustum-shaped part whose cross-sectional area decreases monotonously from its exit side to its incidence side in the cover 60. An optical function film 63 having an optical absorption, reflection, or scattering action is formed on an outer face of the frustum-shaped part.

Abstract: A three-dimensional semiconductor integrated circuit device is provided. A first semiconductor chip includes a solid-state circuit and is smaller than a base, and is stacked on the base. The first chip is buried by a first filling material having approximately the same contour as the base. Buried electrodes that penetrate through the first chip along its thickness direction are formed in the first chip. A second semiconductor chip includes a solid-state circuit and is smaller than the base, and is stacked on the first chip. The second chip is buried by a second filling material having approximately the same contour as the base. Buried electrodes that penetrate through the second chip along its thickness direction are formed in the second chip. The first and second filling materials have processibilities required for forming the buried electrodes and thermal expansion coefficients equivalent to those of the first and second chips, respectively.

Abstract: Image quality degradation due to external light irradiated to an edge section of a transparent cover of a solid-state imaging device and external light propagating in the cover is prevented with a simple structure. A glass cover 60 formed to cover the whole surface of an imaging region 26 of a solid-state imaging element 10 is constituted by a transmission section 60a corresponding to the imaging region 26, and an edge section 60b that surrounds the transmission section 60a outside the transmission section 60a. The edge section 60b of the cover 60 is selectively removed around a periphery of the edge section 60b, thereby forming a frustum-shaped part whose cross-sectional area decreases monotonously from its exit side to its incidence side in the cover 60. An optical function film 63 having an optical absorption, reflection, or scattering action is formed on an outer face of the frustum-shaped part.

Abstract: In a semiconductor package stack module, an LSI (Large Scale Integrated circuit) is mounted, via fine bumps, on a ceramic carrier substrate or a flexible carrier film on which wiring conductors are formed. After a seal resin has been injected, the chip is thinned by, e.g., grinding. A plurality of such carrier substrates or carrier films are connected to each other by bumps via through holes which are electrically connected to the wiring conductors, thereby completing a tridimensional stack module. The module achieves a miniature, thin, dense, low cost, and reliable structure without resorting to a wire bonding system or a TAB (Tape Automated Bonding) system. In addition, the module has a minimum of wiring length and a desirable electric characteristic.

Abstract: A first bump is arranged on an electrode of a semiconductor chip. An opening portion formed at a position corresponding to an electrode on the semiconductor chip, a conductive lead subjected to patterning and arranged in the opening portion, and a second bump for being connected to the outside of the device are formed on a flexible substrate, and the conductive lead and the first bump are connected to each other in the opening portion. An external shape of the flexible substrate is approximately the same as that of the semiconductor chip.

Abstract: A stack module is provided which relieves thermal stress generated in a heat-radiating element and provides improved cooling efficiency. Connection bumps of a plurality of mounting substrates, onto which are mounted semiconductor chips are used to stack the substrates to four levels, three wave-shaped heat-radiating elements, made of copper, being in thermal contact between the semiconductor chips of three of the mounting substrates and the rear surfaces of three of the mounting substrates, making use of the spring elasticity of the heat-radiating elements to establish this thermal contact.

Abstract: A chip carrier semiconductor device comprises a semiconductor chip having a surface on which a plurality of contact pads, a tape carrier overlying the semiconductor chip and a plurality of leads provided on the tape carrier to overly the semiconductor chip, each of the leads having an inside end being provided with at last one bump for bonding a board, the bump being positioned on an inside area of the contact pads.

Abstract: Solder balls are attached to a flexible printed-circuit board which is shaped so as to be able to cover at least an upper surface, a side surface, and a lower surface of an IC chip, and the flexible printed-circuit board is placed on the IC chip. Then, the flexible printed-circuit board is folded over edges of the IC chip, and bonded to outer surfaces of the IC chip by an adhesive sheet. Thereafter, a sealing resin is poured into a gap between the upper surface of the IC chip and the flexible printed-circuit board, and cured, thereby completing a semiconductor package.

Abstract: A device module with a circuit chip and a print-circuit substrate on which a pattern of grooves is formed by selective etching. A liquid sealing material is in the space between the circuit chip and the surface of the substrate, fixing the circuit chip on the surface of the substrate. The circuit chip has a plurality of electrodes arranged in a first pattern, and the substrate has a plurality of connection terminals arranged in the first pattern within a chip mounting area on a surface thereof. Each of the grooves passes between two adjacent connection terminals through the chip mounting area, and both ends of each groove protrudes from the periphery of the chip mounting area. After the circuit chip is placed on the chip mounting area with the respective electrodes corresponding to the connection terminals, a liquid sealing material may be spread more easily into the space between the circuit chip and the substrate by the use of capillary action to provide a more reliable and efficient seal.

Abstract: A device module with a circuit chip and a print-circuit substrate on which a pattern of grooves is formed by selective etching. A liquid sealing material is in the space between the circuit chip and the surface of the substrate, fixing the circuit chip on the surface of the substrate. The circuit chip has a plurality of electrodes arranged in a first pattern, and the substrate has a plurality of connection terminals arranged in the first pattern within a chip mounting area on a surface thereof. Each of the grooves passes between two adjacent connection terminals through the chip mounting area, and both ends of each groove protrudes from the periphery of the chip mounting area. After the circuit chip is placed on the chip mounting area with the respective electrodes corresponding to the connection terminals, a liquid sealing material may be spread more easily into the space between the circuit chip and the substrate by the use of capillary action to provide a more reliable and efficient seal.

Abstract: A chip carrier semiconductor device comprises a semiconductor chip having a surface on which a plurality of contact pads, a tape carrier overlying the semiconductor chip and a plurality of leads provided on the tape carrier to overly the semiconductor chip, each of the leads having an inside end being provided with at last one bump for bonding a board, the bump being positioned on an inside area of the contact pads.

Abstract: A multichip module packaging structure provided over a mother board. A multichip module substrate is mounted over the mother board through a frame member. The frame member is provided to extend successively on a peripheral region of a bottom surface of the substrate and further extend downward from the bottom surface of the substrate. The frame member also has a top portion bonded with the bottom surface of the substrate and a bottom portion bonded with the top surface of the mother substrate so as to form a three dimensional space surrounded by the frame member, the substrate and the mother board. A plurality of semiconductor integrated circuit chips are provided on the bottom surface of the substrate so that the chips are accommodated within the three dimensional space.

Abstract: The present invention relates to a semiconductor casing which permits transmitting ultraviolet rays to a semiconductor chip within the casing. The semiconductor casing includes the substrate formed by a thin metal plate for mounting the semiconductor chip, a ceramic frame fixed to the periphery of the substrate, a ceramic cap which covers the semiconductor chip, is mounted on the ceramic frame and allows transmission of ultraviolet rays, and leads which are sandwiched between the ceramic frame and the ceramic cap to allow the electrical connection of the semiconductor chip.