Patents by Inventor Manabu Takei

Manabu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180158939
    Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.
    Type: Application
    Filed: January 11, 2018
    Publication date: June 7, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Yuichi ONOZAWA, Manabu TAKEI, Akio NAKAGAWA
  • Patent number: 9899503
    Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 20, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Yuichi Onozawa, Manabu Takei, Akio Nakagawa
  • Publication number: 20170301789
    Abstract: In a trench-gate vertical MOSFET, an n-type drift layer and p-type base layer are epitaxially grown on an n+ silicon carbide substrate, and an n++ source region and p++ contact region are provided inside the p-type base layer. The first source electrode contacts the n+ source region, and the second source electrode contacts the p++ contact region. The first source electrode and second source electrode are separated from each other.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 19, 2017
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Manabu TAKEI, Ryuji YAMADA
  • Publication number: 20170236927
    Abstract: A semiconductor device, including a first groove, a second groove and a first impurity region provided on a semiconductor substrate, a second impurity region provided in the first impurity region, a gate electrode provided in the first groove, a first insulating film provided between the first groove and the gate electrode, a second insulating film provided in the second groove, and a third insulating film provided astride tops of the first groove and the second groove. Each of the first and second insulating films has a lower half portion that is thicker than an upper half portion thereof. The lower half portions of the first and second insulating films are connected. The gate electrode has first and second portions thereof respectively contacting the lower and upper half portions of the first insulating film, a width of the first portion being narrower than a width of the second portion.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Yuichi ONOZAWA, Manabu TAKEI
  • Patent number: 9716159
    Abstract: After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: July 25, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Manabu Takei
  • Patent number: 9711628
    Abstract: A semiconductor device has a reduced an on-voltage and uses a gate resistance to improve the trade-off relationship between turn-on loss Eon and dV/dt, and turn-on dV/dt controllability. A floating p+-type region is provided in an n?-type drift layer so as to be spaced from a p-type base region configuring a MOS gate structure. An emitter electrode and the floating p+-type region are electrically connected by an n+-type region provided in the surface layer of a substrate front surface. The n+-type region is covered with a second insulating film which film is covered with an emitter electrode. By an electric field being generated in the n+-type region by the emitter electrode provided on the top of the n+-type region via the second interlayer insulating film, the n+-type region forms a current path which causes holes accumulated in the floating p+-type region to flow to the emitter electrode when turning on.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: July 18, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke Kobayashi, Manabu Takei, Akio Nakagawa
  • Publication number: 20170200805
    Abstract: After a trench is formed, a deposition film is formed on the front surface of a base material and an inner wall of the trench such that a thickness of a portion of the deposition film covering the front surface of the base material is greater than a thickness of a portion of the deposition film covering the inner wall of the trench. The total thickness of the deposition film is then reduced until the inner wall of the trench is exposed, leaving only the portion of the deposition film covering the front surface of the base material. By performing sacrificial oxidation in this state, the thermal oxide film caused by thermal oxidation barely grows at the interface of the front surface of the base material and the deposition film, and thus the thickness of an n+ source region is mostly maintained.
    Type: Application
    Filed: December 9, 2016
    Publication date: July 13, 2017
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Manabu TAKEI
  • Patent number: 9653599
    Abstract: In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: May 16, 2017
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
  • Publication number: 20170108545
    Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.
    Type: Application
    Filed: August 25, 2016
    Publication date: April 20, 2017
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Mitsuru SOMETANI, Manabu TAKEI, Shinsuke HARADA
  • Publication number: 20170110571
    Abstract: In a front surface of a semiconductor base body, a gate trench is disposed penetrating an n+-type source region and a p-type base region to a second n-type drift region. In the second n-type drift region, a p-type semiconductor region is selectively disposed. Between adjacent gate trenches, a contact trench is disposed penetrating the n+-type source region and the p-type base region, and going through the second n-type drift region to the p-type semiconductor region. A source electrode embedded in the contact trench contacts the p-type semiconductor region at a bottom portion and corner portion of the contact trench, and forms a Schottky junction with the second n-type drift region at a side wall of the contact trench.
    Type: Application
    Filed: August 31, 2016
    Publication date: April 20, 2017
    Applicants: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Shinsuke HARADA
  • Publication number: 20160365434
    Abstract: In mesa regions between adjacent trenches disposed in an n?-type drift layer and in which a first gate electrode is disposed via a first gate insulating film, a p-type base region and a floating p+-type region of which a surface is partially covered by a second gate electrode via a second gate insulating film are disposed. An emitter electrode contacts the p-type base region and an n+-type emitter region, and is electrically isolated from first and second gate electrodes and the floating p+-type region by an interlayer insulating film covering the first and second gate electrodes and a portion of the floating p+-type region not covered by the second gate electrode. Thus, turn-on dV/dt controllability by the gate resistance Rg may be improved.
    Type: Application
    Filed: August 29, 2016
    Publication date: December 15, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Yuichi ONOZAWA, Manabu TAKEI, Akio NAKAGAWA
  • Patent number: 9312330
    Abstract: Provision of a super-junction semiconductor device capable of reducing rises in transient on-resistance at the time of repeated switching operation. A super-junction structure is provided that has a striped parallel surface pattern, where a super-junction stripe and a MOS cell 6 stripe are parallel, and a p column Y2 over which no MOS cell 6 stripe is arranged and a p column Y1 over which the MOS cell 6 stripe is arranged are connected at an end.
    Type: Grant
    Filed: July 13, 2010
    Date of Patent: April 12, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Manabu Takei
  • Publication number: 20160064476
    Abstract: A semiconductor device has a reduced an on-voltage and uses a gate resistance to improve the trade-off relationship between turn-on loss Eon and dV/dt, and turn-on dV/dt controllability. A floating p+-type region is provided in an n?-type drift layer so as to be spaced from a p-type base region configuring a MOS gate structure. An emitter electrode and the floating p+-type region are electrically connected by an n+-type region provided in the surface layer of a substrate front surface. The n+-type region is covered with a second insulating film which film is covered with an emitter electrode. By an electric field being generated in the n+-type region by the emitter electrode provided on the top of the n+-type region via the second interlayer insulating film, the n+-type region forms a current path which causes holes accumulated in the floating p+-type region to flow to the emitter electrode when turning on.
    Type: Application
    Filed: August 11, 2015
    Publication date: March 3, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu TAKEI, Akio NAKAGAWA
  • Patent number: 9257544
    Abstract: A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: February 9, 2016
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE and TECHNOLOGY
    Inventors: Manabu Takei, Yoshiyuki Yonezawa
  • Patent number: 9178049
    Abstract: A MOS type semiconductor device wherein on voltage is low, the rate of rise of current at turn-on time is low, and it is possible to hold down the rate of rise of collector current at turn-on time, and reduce radiation noise. The device includes a stripe-shaped plan-view pattern of protruding semiconductor region on an n-type substrate and having a p-type region sandwiched between an upper side n-type first region and a lower side n-type second region, a top flat portion including a depression region with a depth reaching the p-type region, and an inclined portion between the top flat portion and a bottom flat portion around the protruding semiconductor region; and a gate electrode with one end portion of the gate electrode on a surface within the inclined portion, and another end portion on a surface of the lower side n-type second region in the p-type region side vicinity.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 3, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Manabu Takei
  • Publication number: 20150311328
    Abstract: A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 29, 2015
    Applicants: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, FUJI ELECTRIC CO., LTD.
    Inventors: Manabu Takei, Yoshiyuki Yonezawa
  • Patent number: 9087893
    Abstract: A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: July 21, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuhiko Onishi, Mutsumi Kitamura, Akio Sugi, Manabu Takei
  • Publication number: 20140327041
    Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.
    Type: Application
    Filed: July 22, 2014
    Publication date: November 6, 2014
    Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
  • Publication number: 20140319576
    Abstract: In a non-punch-through (NPT) insulated gate bipolar transistor (IGBT), a rear surface structure including a p+ collector layer and a collector electrode is provided on a rear surface of an n? semiconductor substrate and a depletion layer which is spread from a pn junction between a p base region and an n? drift layer when the NPT-IGBT is turned off does not come into contact with the p+ collector layer. A carrier concentration of a region of the n? drift layer that is provided at a depth of 0.3 ?m or less from a pn junction between the n? drift layer and the p+ collector layer is in the range of 30% to 70% of a stored carrier concentration of a region of the n? drift layer that is provided at a depth greater than 0.3 ?m from the pn junction.
    Type: Application
    Filed: July 9, 2014
    Publication date: October 30, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Yusuke KOBAYASHI, Manabu Takei, Akio Nakagawa
  • Patent number: 8847278
    Abstract: A semiconductor device includes an active section for a main current flow and a breakdown withstanding section for breakdown voltage. An external peripheral portion surrounds the active section on one major surface of an n-type semiconductor substrate. The breakdown withstanding section has a ring-shaped semiconductor protrusion, with a rectangular planar pattern including a curved section in each of four corners thereof, as a guard ring. The ring-shaped semiconductor protrusion has a p-type region therein, is sandwiched between a plurality of concavities deeper than the p-type region, and has an electrically conductive film across an insulator film on the surface thereof. Because of this, it is possible to manufacture at low cost a breakdown withstanding structure with which a high breakdown voltage is obtained in a narrow width, wherein there is little drop in breakdown voltage, even when there are variations in a patterning process of a field oxide film.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: September 30, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Manabu Takei, Yusuke Kobayashi