Patents by Inventor Manabu Takei

Manabu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7928932
    Abstract: A display element drive circuit includes a first circuit which holds as a voltage component electric charges based on a gradation signal corresponding to display data, a second circuit which supplies the gradation signal to the electric charge holding circuit at a timing of application of a selection signal, current control type display elements, and a third circuit which generates a driving current based on the voltage component held in the first circuit and supplies the generated driving current to the display element. One of the second and third circuits includes at least one field effect transistor. The field effect transistor includes gate, source and drain electrodes, and a source-side parasitic capacitance formed between the gate and source electrodes and a drain-side parasitic capacitance formed between the gate and drain electrodes of the field effect transistor have different capacitance values.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: April 19, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ikuhiro Yamaguchi, Manabu Takei
  • Publication number: 20110081752
    Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.
    Type: Application
    Filed: May 24, 2010
    Publication date: April 7, 2011
    Applicant: FUJI ELECTRIC SYSTEMS CO., LTD.
    Inventors: Kazuo SHIMOYAMA, Manabu TAKEI, Haruo NAKAZAWA
  • Patent number: 7898507
    Abstract: A display device which displays image information based on display data comprising a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit generates gradation current based on the display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: March 1, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Manabu Takei, Tomoyuki Shirasaki, Ikuhiro Yamaguchi, Tsuyoshi Ozaki, Jun Ogura
  • Patent number: 7863151
    Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: January 4, 2011
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventor: Manabu Takei
  • Patent number: 7855699
    Abstract: A display device includes a display panel having rows of scanning lines and columns of data lines; and a matrix of display pixels near intersections of the scanning lines and the data line. A scanning driver circuit which selects display pixels of rows connected to some of the scanning lines, and a signal driver generates display data for each display pixel. The display panel has scanning line groups which constitute sets of scanning lines through which simultaneous selection is performed by the scanning driver circuit; a plurality of scanning signal lines connected to each of the scanning line groups; and a plurality of data line groups which constitute sets of the data lines corresponding to a line count of the display pixels of the rows connected to each of the scanning line groups within the data lines.
    Type: Grant
    Filed: August 18, 2005
    Date of Patent: December 21, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Tomoyuki Shirasaki, Manabu Takei
  • Publication number: 20100264455
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Application
    Filed: June 28, 2010
    Publication date: October 21, 2010
    Applicant: FUJI ELECTRIC HOLDINGS CO. LTD
    Inventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
  • Publication number: 20100245343
    Abstract: A pixel includes a light emitting element and a driving element connected to the light emitting element. After an initial voltage is applied to one end of a current path of the driving element via the signal line, the pixel driving device acquires the threshold voltage of the driving element based on a voltage value at a terminal of the signal line when the initial voltage is cut off and the relaxation time is elapsed. The voltage-current characteristics of the driving element is acquired based on the voltage value at the terminal of the signal line when the current flows into the current path of the driving element via the signal line. The current gain value of the driving element is acquired based on the threshold voltage of the driving element. The image data is corrected based on the acquired threshold voltage.
    Type: Application
    Filed: March 30, 2010
    Publication date: September 30, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Manabu TAKEI, Jun Ogura, Shunji Kashiyama, Tsuyoshi Ozaki
  • Publication number: 20100245308
    Abstract: Disclosed is a display apparatus including a plurality of display pixels formed of a plurality of first electrodes provided in one surface side of a substrate, a second electrode which faces each of the first electrodes and display functional layers which are provided between each of the first electrodes and the second electrode and a resistive film having a predetermined resistivity in which one surface side is provided so as to face the other surface side of the second electrode having a predetermined space above the upper surface of a partition wall layer to define a forming region for each of the display pixels and which is disposed so as to be conductive to the other surface side of the second electrode by a pressure applied from outside, and the second electrode constructing the display pixels is double used as an electrode for detecting a position where the pressure is applied.
    Type: Application
    Filed: March 29, 2010
    Publication date: September 30, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventor: Manabu TAKEI
  • Patent number: 7795621
    Abstract: A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data lines, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover at least a part of the gate electrode of each of the thin film transistors.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: September 14, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Ikuhiro Yamaguchi, Manabu Takei, Motohiko Yoshida
  • Patent number: 7791568
    Abstract: A display panel (110) includes a plurality of optical elements (OEL) each having a pair of electrodes and performing an optical operation according to current passing between the pair of electrodes, a current line (DL), a switch circuit (Tr2) that passes a write current (Ia) with a predetermined current value through the current line (DL) during a selection time (Tse) and stops passing current during a non-selection time (Tnse), and a current storage circuit (Tr1, Tr3, Cs, Cp) that stores current data according to the current value of the write current (Ia) passing through the current line (DL) during the selection time (Tse) and that supplies a drive current (Ib) having a current value, which is obtained by subtracting a predetermined offset current (Ioff) from the current value of the stored write current (Ia), to the optical elements (OEL) during the non-selection time (Tnse).
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: September 7, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hiroyasu Yamada, Manabu Takei
  • Patent number: 7790519
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Grant
    Filed: May 29, 2007
    Date of Patent: September 7, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Patent number: 7776672
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Grant
    Filed: March 27, 2006
    Date of Patent: August 17, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
  • Patent number: 7741192
    Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: June 22, 2010
    Assignee: Fuji Electric Systems Co., Ltd.
    Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
  • Publication number: 20100140657
    Abstract: A semiconductor device according to the invention includes n-type semiconductor substrate 1; trenches 15 formed in the surface portion of semiconductor substrate 1; a protruding semiconductor region between trenches 15; p-type base layer 2 in the protruding semiconductor region, p-type base layer 2 being positioned as deep as or shallower than trench 15; an n++-type emitter region or a source region in the surface portion of p-type base layer 2; gate insulator film 4a on the first side wall of the protruding semiconductor region; and gate electrode 6 on gate insulator film 4a. Trench 15 is from 0.5 ?m to 3.0 ?m deep and the short side of trench 15 is 1.0 ?m or longer. The short side of the protruding semiconductor region is from 0.5 ?m to 3.0 ?m long. Gate electrode 6 contains electrically conductive polycrystalline silicon as its main component. Gate electrode 6 is from 0.2 ?m to 1.0 ?m thick.
    Type: Application
    Filed: November 12, 2009
    Publication date: June 10, 2010
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Manabu TAKEI
  • Publication number: 20100134475
    Abstract: A pixel driving device has a voltage impressing circuit that outputs a reference voltage that exceeds a threshold voltage of a drive transistor, a voltage measurement circuit, and a property parameter acquisition circuit that acquires a property parameter related to an electronic property of a pixel. The pixel driving device impresses the reference voltage on the pixel that has a light emitting element and the drive transistor. The voltage measurement circuit acquires voltage of a signal line, as measured voltages, after each of a plurality of the settling times elapsing from the time when the reference voltage is cut. The property parameter acquisition circuit acquires, as property parameters, the threshold voltage and a current amplification factor of drive transistor based on values of a plurality of measured voltages acquired by the voltage measurement circuit.
    Type: Application
    Filed: November 27, 2009
    Publication date: June 3, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: JUN OGURA, Manabu Takei, Shunji Kashiyama
  • Publication number: 20100134469
    Abstract: A light emitting device has a plurality of pixels, each of which includes a drive transistor, a light emitting element and signal lines, a property parameter acquisition circuit which acquires property parameter, a signal correction circuit that generates a corrected gradation signal by correcting the image data based on the property parameter, and a drive signal impressing circuit that impresses a drive signal, generated based on the corrected gradation signal, on the pixel to drive it. The property parameter is constituted of a threshold voltage, a current amplification factor and its irregularity of the drive transistor, and is acquired based on measured voltages of the signal lines after each of a plurality of predetermined settling times elapses from the time when the light emitting device cuts off a voltage subsequent to impressing the voltage on each pixel for a predetermined length of time.
    Type: Application
    Filed: November 27, 2009
    Publication date: June 3, 2010
    Inventors: JUN OGURA, Manabu Takei, Shunji Kashiyama
  • Publication number: 20100134468
    Abstract: A pixel driving device in which, after a reference voltage exceeds a threshold voltage of a drive transistor is impressed through the signal lines on each pixel equipping a light emitting element and the drive transistor, set the signal lines in a state of high impedance, and acquires a voltage value of one end of the signal lines subsequent to a predetermined settling time elapsing, and acquires the threshold voltage of the drive transistor for each pixel and the current amplification factor of the pixel drive circuit as a first property parameter based on acquired voltage values at the time a plurality of first settling times longer than a predetermined value and acquires an irregularity parameter indicating the irregularity in the current amplification factor based on the value of the first property parameter and the measured voltage value acquired at the time shorter than the predetermined value.
    Type: Application
    Filed: November 27, 2009
    Publication date: June 3, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: Jun OGURA, Manabu TAKEI, Shunji KASHIYAMA
  • Publication number: 20100134482
    Abstract: A pixel driving device for drive control of pixels, has a image data conversion circuit for generating an original gradation signal by converting an image data, based on a preset conversion property, a signal correction circuit for outputting a corrected gradation signal by adding a correction value acquired based on an electric property parameter of a pixel to the original gradation signal, and a drive signal impressing circuit for impressing a voltage signal corresponding to the corrected gradation signal on one end of a signal line. The original gradation signal has a value that corresponds to a gradation value of the image data and the maximum value of the original gradation signal is set to a value equal to or smaller than a value acquired by subtracting a value corresponding to the correction value from a maximum value in an input range of the drive signal impressing circuit.
    Type: Application
    Filed: November 27, 2009
    Publication date: June 3, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventors: JUN OGURA, Manabu Takei, Shunji Kashiyama
  • Publication number: 20100093164
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Application
    Filed: October 8, 2009
    Publication date: April 15, 2010
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Haruo NAKAZAWA, Kazuo SHIMOYAMA, Manabu TAKEI
  • Publication number: 20100079420
    Abstract: A pixel drive device that drives a pixel array including pixels connected to input/output terminals includes: a connection unit including connection terminals whose number is fewer than a number of the input/output terminals; and a connection switching unit that switches connection between the connection terminals and the input/output terminals. The input/output terminals of the pixel array are divided into a plurality of blocks each including a predetermined number of input/output terminals that is equal to/smaller than the number of connection terminals. The connection switching unit sequentially connects the connection terminals and the input/output terminals of each of the blocks, and sets the connection order of connecting the input/output terminals of each block to the connection terminals, such that adjoining two of the input/output terminals belonging to adjoining two of the blocks are connected to the same one of the connection terminals.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 1, 2010
    Applicant: Casio Computer Co., Ltd
    Inventors: Manabu Takei, Tsuyoshi Ozaki, Shunji Kashiyama