Patents by Inventor Manabu Takei

Manabu Takei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070262362
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Application
    Filed: July 20, 2007
    Publication date: November 15, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Setsuko WAKIMOTO, Manabu TAKEI, Shinji FUJIKAKE
  • Publication number: 20070235755
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Application
    Filed: June 14, 2007
    Publication date: October 11, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventor: Manabu TAKEI
  • Publication number: 20070224769
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Application
    Filed: May 29, 2007
    Publication date: September 27, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Patent number: 7262100
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: August 28, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Patent number: 7262478
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: August 28, 2007
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20070158740
    Abstract: A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.
    Type: Application
    Filed: November 28, 2006
    Publication date: July 12, 2007
    Applicant: FUJI ELECTRIC HOLDINGS CO., LTD.
    Inventors: Koh Yoshikawa, Akio Sugi, Kouta Takahashi, Manabu Takei, Haruo Nakazawa, Noriyuki Iwamuro
  • Publication number: 20070072359
    Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
    Type: Application
    Filed: November 9, 2006
    Publication date: March 29, 2007
    Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.
    Inventors: Manabu TAKEI, Tatsuya NAITO, Michio NEMOTO
  • Patent number: 7157785
    Abstract: A semiconductor device is disclosed that reduces the reverse leakage current caused by reverse bias voltage application and reduces the on-voltage of the IGBT. A two-way switching device using the semiconductor devices is provided, and a method of manufacturing the semiconductor device is disclosed. The reverse blocking IGBT reduces the reverse leakage current and the on-voltage by bringing portions of an n?-type drift region 1 that extend between p-type base regions and an emitter electrode into Schottky contact to form Schottky junctions.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 2, 2007
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Manabu Takei, Tatsuya Naito, Michio Nemoto
  • Publication number: 20060249797
    Abstract: On the top surface of a thin semiconductor wafer, top surface structures forming a semiconductor chip are formed. The top surface of the wafer is affixed to a supporting substrate with a double-sided adhesive tape. Then, from the bottom surface of the thin semiconductor wafer, a trench, which becomes a scribing line, is formed by wet anisotropic etching so that side walls of the trench are exposed. On the side walls of the trench with the crystal face exposed, an isolation layer with a conductivity type different from that of the semiconductor wafer for holding a reverse breakdown voltage is formed simultaneously with a collector region of the bottom surface diffused layer by ion implantation, followed by annealing with laser irradiation. The side walls form a substantially V-shaped or trapezoidal-shaped cross section, with an angle of the side wall relative to the supporting substrate being 30-70°. The double-sided adhesive tape is then removed from the top surface to produce semiconductor chips.
    Type: Application
    Filed: March 27, 2006
    Publication date: November 9, 2006
    Applicant: FUJI ELECTRIC HOLDING CO., LTD.
    Inventors: Haruo Nakazawa, Kazuo Shimoyama, Manabu Takei
  • Publication number: 20060192204
    Abstract: A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data lines, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover at least a part of the gate electrode of each of the thin film transistors.
    Type: Application
    Filed: February 16, 2006
    Publication date: August 31, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Ikuhiro Yamaguchi, Manabu Takei, Motohiko Yoshida
  • Publication number: 20060186508
    Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.
    Type: Application
    Filed: April 4, 2006
    Publication date: August 24, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Michio Nemoto, Manabu Takei, Tatsuya Naito
  • Patent number: 7049674
    Abstract: A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n? drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: May 23, 2006
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Michio Nemoto, Manabu Takei, Tatsuya Naito
  • Publication number: 20060076583
    Abstract: A semiconductor device has a MOS gate side surface structure, including a gate electrode filling a trench formed in a semiconductor substrate with an insulator film between the trench and the gate electrode, a gate insulator film covering the surface of the gate electrode, a buffer region of one conductivity type in contact with the semiconductor substrate, a base region of the other conductivity type adjacent to the buffer region on the gate insulator film, and an emitter region of the one conductivity type adjacent to the base region on the side opposite to the buffer region. The semiconductor device and the method of manufacturing thereof can further improve the tradeoff between the on-voltage and the turn-off loss by increasing the amount of electrons injected from a cathode on the surface to increase an amount of carriers on the cathode side in a stable turned-on state of the device.
    Type: Application
    Filed: September 2, 2005
    Publication date: April 13, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Setsuko Wakimoto, Manabu Takei, Shinji Fujikake
  • Publication number: 20060066219
    Abstract: A display panel includes a transistor array substrate which has a plurality of transistors including at least a driving transistor, and a plurality of pixel electrodes electrically connected to the driving transistor of the plurality of transistors. A plurality of light-emitting layers are provided on the pixel electrodes. A counter electrode is provided on the light-emitting layers. Each of a plurality of interconnections is arranged between the pixel electrodes adjacent to each other and electrically connected to the counter electrode.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 30, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Satoru Shimoda, Manabu Takei, Tomoyuki Shirasaki, Jun Ogura
  • Publication number: 20060066644
    Abstract: A display element drive circuit includes a first circuit which holds as a voltage component electric charges based on a gradation signal corresponding to display data, a second circuit which supplies the gradation signal to the electric charge holding circuit at a timing of application of a selection signal, current control type display elements, and a third circuit which generates a driving current based on the voltage component held in the first circuit and supplies the generated driving current to the display element. One of the second and third circuits includes at least one field effect transistor. The field effect transistor includes gate, electrode and drain electrodes, and a source-side parasitic capacitance formed between the gate and source electrodes and a drain-side parasitic capacitance formed between the gate and drain electrodes of the field effect transistor have different capacitance values.
    Type: Application
    Filed: September 26, 2005
    Publication date: March 30, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Ikuhiro Yamaguchi, Manabu Takei
  • Publication number: 20060061526
    Abstract: A drive circuit which drives an optical element in accordance with a gradation signal corresponding to display data includes an electric charge holding circuit which holds electric charges based on the gradation signal as a voltage component, and a driving current control circuit which generates a driving current based on the voltage component held in the electric charge holding circuit and supplies the generated driving current to the optical element. The driving current control circuit has at least one double-gate type thin film transistor. The transistor includes a semiconductor layer, a first gate electrode provided above the semiconductor layer, a second gate electrode provided below the semiconductor layer, and a source and drain electrodes provided on both end portion sides of the semiconductor layer.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 23, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Tomoyuki Shirasaki, Ikuhiro Yamaguchi, Manabu Takei
  • Publication number: 20060049434
    Abstract: A semiconductor device and method of manufacturing the same includes an n?-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n?-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.
    Type: Application
    Filed: September 2, 2005
    Publication date: March 9, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventor: Manabu Takei
  • Publication number: 20060038206
    Abstract: A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer.
    Type: Application
    Filed: August 19, 2005
    Publication date: February 23, 2006
    Applicant: Fuji Electric Holdings Co., Ltd.
    Inventors: Kazuo Shimoyama, Manabu Takei, Haruo Nakazawa
  • Publication number: 20060017668
    Abstract: A display device includes a display panel having rows of scanning lines and columns of data lines; and a matrix of display pixels near intersections of the scanning lines and the data line. A scanning driver circuit which selects display pixels of rows connected to some of the scanning lines, and a signal driver generates display data for each display pixel. The display panel has scanning line groups which constitute sets of scanning lines through which simultaneous selection is performed by the scanning driver circuit; a plurality of scanning signal lines connected to each of the scanning line groups; and a plurality of data line groups which constitute sets of the data lines corresponding to a line count of the display pixels of the rows connected to each of the scanning line groups within the data lines.
    Type: Application
    Filed: August 18, 2005
    Publication date: January 26, 2006
    Applicant: Casio Computer Co., Ltd.
    Inventors: Tomoyuki Shirasaki, Manabu Takei
  • Publication number: 20050280613
    Abstract: A display device which displays image information based on display data comprising a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit generates gradation current based on the display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.
    Type: Application
    Filed: June 16, 2005
    Publication date: December 22, 2005
    Applicant: Casio Computer Co., Ltd.
    Inventors: Manabu Takei, Tomoyuki Shirasaki, Ikuhiro Yamaguchi, Tsuyoshi Ozaki, Jun Ogura