Abstract: A service start method is a service start method executed by a communication system, and the service start method includes: a step of acquiring identification information or authentication information of a device, a customer, or a service; a step of making authentication of the device, the customer, or the service to succeed when the identification information or the authentication information has been acquired together with information that is associated with the customer or a customer's location in advance, or when the identification information or the authentication information has been acquired from a terminal or a line that is associated with the customer in advance; and a step of starting provision of the service for the device for which the authentication has succeeded.

Abstract: A high withstand voltage isolation region has a first diffusion layer of a second conductivity type formed on a principal surface of a semiconductor substrate. The high withstand voltage MOS has a second diffusion layer of the second conductivity type formed on the principal surface of the semiconductor substrate. A low side circuit region has a third diffusion layer of a first conductivity type formed on the principal surface of the semiconductor substrate. A fourth diffusion layer of the first conductivity type having a higher impurity concentration than the semiconductor substrate is formed on the principal surface of the semiconductor substrate exposed between the first diffusion layer and the second diffusion layer. The fourth diffusion layer extends from the high side circuit region to the low side circuit region and does not contact the third diffusion layer.

Abstract: A RESURF isolation structure surrounds an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. The high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a plurality of field plates (9,19a,19b,19c). An inner end of the field plate (19c) of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate (19b) of the high-voltage N-ch MOS located closest to the low-side circuit region.

Abstract: Provided is a semiconductor device including: an N-type diffusion layer being a second region, formed in a surface portion of a P-type diffusion layer being a first region, to function as a RESURF region; an N-type buried diffusion layer being a third region formed in a bottom portion of the second region, close to a high-side circuit; and a MOSFET using the second region as a drift layer. The MOSFET includes a thermal oxide film formed between an N-type diffusion layer being a fourth region serving as a drain region and an N-type diffusion layer being a sixth region serving as a source region, and an N-type diffusion layer being a seventh region formed below the thermal oxide film. The seventh region has an end portion close to a low-side circuit, being closer to the low-side circuit than an end portion of the third region close to the low-side circuit.

Abstract: The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N+-type diffusion region, an N-type diffusion region, a P+-type diffusion region, a P-type diffusion region, an N+-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N+-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N+-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N+-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N+-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.

Abstract: A communication apparatus includes: a memory that stores, first data on firmware before update, second data on firmware after the update, and a table in which the first data or the second data is associated with an address where the first data or the second data is positioned; and a processor that executes processing based on the first data or the second data positioned at the address defined in the table.

Abstract: A communication apparatus includes: an execution unit configured to execute at least either switching of a path of a signal or transmission of the signal on the path; and an instruction unit, wherein the instruction unit includes a first interface configured to send a command to the execution unit, and the execution unit includes a second interface configured to receive the command, and executes at least one of the switching of the path, start of the transmission of the signal, or suspension of the transmission of the signal according to the command either immediately, or after a configured time period or a predetermined time period elapses.

Abstract: The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n? type drift region and not penetrating a SiC substrate; an n+ type side surface diffusion region formed on each side surface of the first trench; an n+ type bottom diffusion region formed under the n? type drift region and in contact with the n+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n? type drift region at regular spacings of 0.4 ?m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

Abstract: Provided is a method for determining the ratio of a measurement object substance to a comparison object substance using a measuring reagent for the measurement object substance. The method makes it possible to easily determine, from an absorbance measured value, the ratio of the measurement object substance to the comparison object substance, using a single calibration curve (multiplexed calibration curve) which is not dependent on the concentration of the comparison object substance.

Abstract: A semiconductor device wherein a high-side circuit region, a low-side circuit region, and a high-voltage MOS that transmits a signal between the high-side circuit region and the low-side circuit region are provided on one semiconductor substrate, includes: a high-voltage isolation region isolating the high-side circuit region and the low-side circuit region from each other; a trench isolation isolating the high-voltage MOS and the high-voltage isolation region from each other; an N-type diffusion layer provided on an upper surface of the semiconductor substrate in the high-side circuit region and the high-voltage isolation region; and an N-type region provided on both sides of the trench isolation and having an impurity concentration lower than an impurity concentration of the N-type diffusion layer.

Abstract: A RESURF isolation structure surrounds an outer periphery of the high-side circuit region to isolate the high-side circuit region and the low-side circuit region from each other. The RESURF isolation structure includes a high-voltage isolation region, a high-voltage N-ch MOS, and a high-voltage P-ch MOS. The high-voltage isolation region, the high-voltage N-ch MOS, and the high-voltage P-ch MOS include a plurality of field plates (9,19a,19b,19c). An inner end of the field plate (19c) of the high-voltage P-ch MOS located closest to the low-side circuit region is positioned closer to the low-side circuit region than an inner end of the field plate (19b) of the high-voltage N-ch MOS located closest to the low-side circuit region.

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing thereof capable of relaxing a level difference thereon. A semiconductor device according to the present invention includes a first interlayer insulating film having a first opening, and a second interlayer insulating film having a second opening wherein a following expression is satisfied: (H2?H1)/((W2?W1)/2)?3.6 where, in sectional view, W1 represents a width of the first opening, W2 represents a width of the second opening, H1 represents a minimum value of a height from a surface of the semiconductor substrate to a surface of the third interlayer insulating film in the second opening, and H2 represents a height from the surface of the semiconductor substrate to the surface of the third interlayer insulating film in an end of the second opening.

Abstract: The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n? type drift region and not penetrating a SiC substrate; an n+ type side surface diffusion region formed on each side surface of the first trench; an n+ type bottom diffusion region formed under the n? type drift region and in contact with the n+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n? type drift region at regular spacings of 0.4 ?m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

Abstract: A communication apparatus includes a packet reception unit; a packet transmission unit; and a processing sequence control unit that controls a processing sequence, and the processing sequence control unit includes a packet holding unit; function instances for respective function files including groups of procedures and groups of variables; an instance information management unit that holds instance information including function instance identifiers identifying the function instances, procedure identifiers identifying the procedures belonging to the function instances, and memory addresses of the procedures; an execution sequence information management unit that holds execution sequence information that associates the function instance identifiers, the procedure identifiers, return values of the procedures, and procedures belonging to function instances that are to be executed next; and a function execution unit that, on the basis of the execution sequence information and the instance information, calls a pro

Abstract: An object of the present invention is to provide a semiconductor device and a method of manufacturing thereof capable of relaxing a level difference thereon. A semiconductor device according to the present invention includes a first interlayer insulating film having a first opening, and a second interlayer insulating film having a second opening wherein a following expression is satisfied: (H2?H1)/((W2?W1)/2)?3.6 where, in sectional view, W1 represents a width of the first opening, W2 represents a width of the second opening, H1 represents a minimum value of a height from a surface of the semiconductor substrate to a surface of the third interlayer insulating film in the second opening, and H2 represents a height from the surface of the semiconductor substrate to the surface of the third interlayer insulating film in an end of the second opening.

Abstract: A communication processing device including: a memory that stores data relating to a pre-update firmware, and second data relating to a post-update firmware, and that stores first reference destination address indicating the storage area of reference destination included in the first data in association with the reference destination; a rewriting unit configured to rewrite at least some of the first reference destination address stored in the memory with second reference destination address indicating the storage area of the reference destination in the second data; and a control unit configured to, when referring to the reference destination in the first data, refer to the second data on the basis of the second reference destination address stored in the memory.

Abstract: An object is to provide a technique for enhancing the breakdown voltage of a semiconductor device. A semiconductor circuit includes a first resistor, a second resistor, a third resistor, a MOSFET, and an inverter. The first resistor, the second resistor, and the third resistor are connected in series between a power supply and a ground corresponding to the reference voltage of a low-side circuit. The MOSFET is connected to the third resistor in parallel between the second resistor and the ground, and has a gate electrically connected to the low-side circuit. The inverter is electrically connected between a connection point and the high-side circuit, the connection point being located between the first resistor and the second resistor.

Abstract: An object is to provide a technique for enhancing the breakdown voltage of a semiconductor device. A semiconductor circuit includes a first resistor, a second resistor, a third resistor, a MOSFET, and an inverter. The first resistor, the second resistor, and the third resistor are connected in series between a power supply and a ground corresponding to the reference voltage of a low-side circuit. The MOSFET is connected to the third resistor in parallel between the second resistor and the ground, and has a gate electrically connected to the low-side circuit. The inverter is electrically connected between a connection point and the high-side circuit, the connection point being located between the first resistor and the second resistor.

Abstract: A lateral high-voltage transistor includes: a semiconductor substrate; a semiconductor layer being provided on one main surface of the semiconductor substrate; a source region being provided selectively in a surface of the semiconductor layer; a drain region being provided selectively in the surface of the semiconductor layer; a gate electrode provided on a part of the semiconductor layer between the source region and the drain region with interposition of the gate insulating film; and a drift region being provided selectively in the surface of the semiconductor layer. The drift region includes a stripe-shaped diffusion layer extending in parallel with a direction from the drain region toward the source region. The stripe-shaped diffusion layer includes linear diffusion layers each including stripe-shaped diffusion regions that are adjacent to each other such that double diffusion occurs in a portion where the stripe-shaped diffusion regions are adjacent to each other.

Abstract: A method of manufacturing a semiconductor device, includes the steps of forming a top surface nitride film on a top surface of a substrate and a bottom surface nitride film on a bottom surface of the substrate, forming a protective film on the top surface nitride film, removing the bottom surface nitride film by wet etching while the top surface nitride film is being protected by the protective film, removing the protective film after the removing of the bottom surface nitride film, patterning the top surface nitride film so as to form an opening in the top surface nitride film, and forming a second oxide film on the bottom surface of the substrate while forming a first oxide film on a surface portion of the substrate which is exposed by the opening.