Patents by Inventor Manish Chandhok
Manish Chandhok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12218052Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.Type: GrantFiled: October 27, 2023Date of Patent: February 4, 2025Assignee: Intel CorporationInventors: Richard E. Schenker, Robert L Bristol, Kevin L. Lin, Florian Gstrein, James M. Blackwell, Marie Krysak, Manish Chandhok, Paul A Nyhus, Charles H. Wallace, Curtis W. Ward, Swaminathan Sivakumar, Elliot N. Tan
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Publication number: 20250006810Abstract: Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. The underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.Type: ApplicationFiled: June 29, 2023Publication date: January 2, 2025Applicant: Intel CorporationInventors: Shao-Ming Koh, Manish Chandhok, Marvin Paik, Shahidul Haque, Jason Klaus, Asad Iqbal, Patrick Morrow, Nikhil Mehta, Alison Davis, Sean Pursel, Steven Shen, Christopher Rochester, Matthew Prince
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Patent number: 12176214Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member.Type: GrantFiled: October 25, 2021Date of Patent: December 24, 2024Assignee: Intel CorporationInventors: Kevin Lin, Rahim Kasim, Manish Chandhok, Florian Gstrein
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Publication number: 20240395815Abstract: Integrated circuit structures having metal-containing fin isolation regions are described. In an example, an integrated circuit structure includes a vertical stack of horizontal nanowires over a first sub-fin. A gate structure is over the vertical stack of horizontal nanowires and on the first sub-fin. A dielectric structure is laterally spaced apart from the gate structure. The dielectric structure is not over a channel structure but is on a second sub-fin. A gate cut is between the gate structure and the dielectric structure. A dielectric gate cut plug is in the gate cut. The dielectric gate plug includes a metal-containing dielectric material.Type: ApplicationFiled: May 23, 2023Publication date: November 28, 2024Inventors: Leonard P. GULER, Manish CHANDHOK, Tsuan-Chung CHANG, Robert JOACHIM, Peter NGUYEN, Lily MAO, Erik SKIBINSKI
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Patent number: 12131991Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.Type: GrantFiled: February 14, 2022Date of Patent: October 29, 2024Assignee: Intel CorporationInventors: Manish Chandhok, Leonard Guler, Paul Nyhus, Gobind Bisht, Jonathan Laib, David Shykind, Gurpreet Singh, Eungnak Han, Noriyuki Sato, Charles Wallace, Jinnie Aloysius
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Publication number: 20240304543Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: ApplicationFiled: May 17, 2024Publication date: September 12, 2024Applicant: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Patent number: 12087836Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.Type: GrantFiled: October 20, 2023Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Rami Hourani, Richard Vreeland, Giselle Elbaz, Manish Chandhok, Richard E. Schenker, Gurpreet Singh, Florian Gstrein, Nafees Kabir, Tristan A. Tronic, Eungnak Han
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Patent number: 12087594Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.Type: GrantFiled: December 17, 2020Date of Patent: September 10, 2024Assignee: Intel CorporationInventors: Gurpreet Singh, Eungnak Han, Manish Chandhok, Richard E Schenker, Florian Gstrein, Paul A. Nyhus, Charles Henry Wallace
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Patent number: 12080639Abstract: Contact over active gate structure with metal oxide layers are described are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A portion of one of the plurality of trench contact structures has a metal oxide layer thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on the metal oxide layer.Type: GrantFiled: September 23, 2019Date of Patent: September 3, 2024Assignee: Intel CorporationInventors: Rami Hourani, Manish Chandhok, Richard E. Schenker, Florian Gstrein, Leonard P. Guler, Charles H. Wallace, Paul A. Nyhus, Curtis Ward, Mohit K. Haran, Reken Patel
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Publication number: 20240290651Abstract: Described herein are IC devices include vias deposited in a regular array, e.g., a hexagonal array, and processes for depositing vias in a regular array. The process includes depositing a guiding pattern over a metal grating, depositing a diblock copolymer over the guiding pattern, and causing the diblock copolymer to self-assemble such one polymer forms an array of cylinders over metal portions of the metal grating. The polymer layer can be converted into a hard mask layer, with one hard mask material forming the cylinders, and a different hard mask material surrounding the cylinders. A cylinder can be selectively etched, and a via material deposited in the cylindrical hole to form a via.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicant: Intel CorporationInventors: Florian Gstrein, Eungnak Han, Manish Chandhok, Gurpreet Singh
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Publication number: 20240219842Abstract: Numerous embodiments of a method for developing a photoresist material are described. In one embodiment of the present invention, a photoresist layer is disposed over a substrate. The photoresist layer has a bulk region to form a first region and a second region. A photoresist developer made of a tetra-alkyl ammonium hydroxide compound is applied to the photoresist layer to react only with substantial portions of the first region and to prevent penetration of the developer solution into the bulk portion near the second region.Type: ApplicationFiled: September 30, 2004Publication date: July 4, 2024Inventors: Manish Chandhok, Wang Yueh, Heidi Cao
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Patent number: 12027458Abstract: IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.Type: GrantFiled: June 15, 2022Date of Patent: July 2, 2024Assignee: Intel CorporationInventors: Kevin Lin, Noriyuki Sato, Tristan Tronic, Michael Christenson, Christopher Jezewski, Jiun-Ruey Chen, James M. Blackwell, Matthew Metz, Miriam Reshotko, Nafees Kabir, Jeffery Bielefeld, Manish Chandhok, Hui Jae Yoo, Elijah Karpov, Carl Naylor, Ramanan Chebiam
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Publication number: 20240203868Abstract: Metal lines are formed through serial DSA processes. A first DSA process may define a pattern of first hard masks. First metal lines are fabricated based on the first hard masks. A metal cut crossing one or more first metal lines may be formed. A width of the metal cut is no greater than a pitch of the first metal lines. After the metal cut is formed, a second DSA process is performed to define a pattern of second hard masks. Edges of a second hard mask may align with edges of a first metal line. An insulator may be formed around a second hard mask to form an insulative structure. An axis of the insulative structure may be aligned with an axis of a first metal line. Second metal lines are formed based on the second hard masks and have a greater height than the first metal lines.Type: ApplicationFiled: December 15, 2022Publication date: June 20, 2024Applicant: Intel CorporationInventors: Gurpreet Singh, Manish Chandhok, David Nathan Shykind, Richard E. Schenker, Florian Gstrein, Eungnak Han, Nafees Aminul Kabir, Sean Michael Pursel, Nityan Labros Nair, Robert Seidel
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Publication number: 20240204083Abstract: DSA-based spacers and liners can provide shorting margins for vias connected to conductive structures. Self-assembly of a diblock copolymer may be performed over a layer including conductive structures and insulative structures separating the conductive structures from each other. Spacers may be formed based on the self-assembly of the diblock copolymer. Each spacer includes an electrical insulator and is over an insulative structure. Each liner may wrap around one or more side surfaces of a spacer. Each pair of spacer and liner constitutes an insulative spacing structure that provides a shorting margin to avoid short between a via and a conductive structure not connected to the via. The insulative spacing structures may include a different electrical insulator from the insulative structures. The conductive structures may be arranged in parallel along a direction and have the same or similar heights in the direction and function as different contacts of a device.Type: ApplicationFiled: December 15, 2022Publication date: June 20, 2024Applicant: Intel CorporationInventors: Gurpreet Singh, Manish Chandhok, Florian Gstrein, Charles Henry Wallace, Eungnak Han, Leonard P. Guler
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Publication number: 20240194672Abstract: An IC device may include a first conductive structure in a first section and a second conductive structure in a second section. The second conductive structure is in parallel with the first conductive structure in a first direction. A dimension of the second conductive structure in a second direction perpendicular to the first direction is greater than a dimension of the first conductive structure in the second direction. The first conductive structure may be coupled to a channel region of a transistor. The second conductive structure may be coupled to a channel region of another transistor. A first structure comprising a first dielectric material may be over the first conductive structure. A second structure comprising a second dielectric material may be over the second section. A third structure comprising the first dielectric material may be over the second conductive structure and be at least partially surrounded by the second structure.Type: ApplicationFiled: December 12, 2022Publication date: June 13, 2024Applicant: Intel CorporationInventors: Bharath Bangalore Rajeeva, Manish Chandhok, Gurpreet Singh, Kevin Huggins, Eungnak Han, Florian Gstrein, Marko Radosavljevic
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Publication number: 20240170394Abstract: Integrated circuitry comprising an interconnect level with multi-height lines contacted by complementary multi-height vias. In some examples, a first line of a taller height is contacted by a first via of a shorter height while a second line of a shorter height is contacted by a second via of a taller height. The first and second vias and first and second lines may be subtractively defined concurrently from a same stack of conductive material layers such that the first via comprises a first conductive material layer, and the first line comprises second and third conductive material layers while the second via comprises the first and second conductive material layers and the second line comprises the third conductive material layer.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Applicant: Intel CorporationInventors: Elijah Karpov, June Choi, Manish Chandhok, Miriam Reshotko, Matthew Metz
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Patent number: 11990403Abstract: Dielectric helmet-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. In an example, a semiconductor structure includes a substrate. A plurality of alternating first and second conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed in an inter-layer dielectric (ILD) layer disposed above the substrate. A dielectric layer is disposed on an uppermost surface of the first conductive line types but not along sidewalls of the first conductive line types, and is disposed along sidewalls of the second conductive line types but not on an uppermost surface of the second conductive line types.Type: GrantFiled: March 30, 2021Date of Patent: May 21, 2024Assignee: Intel CorporationInventors: Kevin L. Lin, Richard E. Schenker, Jeffery D. Bielefeld, Rami Hourani, Manish Chandhok
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Publication number: 20240114693Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Applicant: Intel CorporationInventors: Christopher M. Neumann, Brian Doyle, Nazila Haratipour, Shriram Shivaraman, Sou-Chi Chang, Uygar E. Avci, Eungnak Han, Manish Chandhok, Nafees Aminul Kabir, Gurpreet Singh
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Publication number: 20240088218Abstract: Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices.Type: ApplicationFiled: September 13, 2022Publication date: March 14, 2024Applicant: Intel CorporationInventors: Shao-Ming Koh, Leonard P. Guler, Gurpreet Singh, Manish Chandhok, Matthew J. Prince
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Publication number: 20240071917Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.Type: ApplicationFiled: October 27, 2023Publication date: February 29, 2024Inventors: Richard E. SCHENKER, Robert L. BRISTOL, Kevin L. LIN, Florian GSTREIN, James M. BLACKWELL, Marie KRYSAK, Manish CHANDHOK, Paul A. NYHUS, Charles H. WALLACE, Curtis W. WARD, Swaminathan SIVAKUMAR, Elliot N. TAN