Patents by Inventor Mansour Keramat
Mansour Keramat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8121221Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: GrantFiled: July 15, 2008Date of Patent: February 21, 2012Assignee: Nvidia CorporationInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 7977762Abstract: An integrated circuit (IC) is disclosed to include a central area of the IC that is partitioned into a first section containing at least one digital circuit and a second section containing at least one analog circuit; and a guard strip (or shield) that is within the central area and that is positioned within between the digital circuit and the analog circuit. The shield or guard strip comprises of n-well and p-tap regions that separate digital and analog circuits.Type: GrantFiled: December 9, 2008Date of Patent: July 12, 2011Assignee: Alvand Technologies, Inc.Inventors: Mansour Keramat, Mehrdad Heshami, Syed S. Islam
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Patent number: 7920006Abstract: In one embodiment of the present invention, a clock generator circuit receives a clock signal having a period. The clock signal is employed by a digital circuit that is resident on the same substrate as an analog circuit, the digital circuit generates disturbance climaxes at clock edges that propagate through the substrate to the analog circuit. A clock generator circuit generates a plurality of clock signals, with each clock signal having a unique rate, wherein during a temporal gap, defined by the time between a last disturbance climax and a next sampling time of the clock signal, clock edges of any of the plurality of clock signals are avoided.Type: GrantFiled: December 18, 2008Date of Patent: April 5, 2011Assignee: Alvand Technologies, Inc.Inventors: Mansour Keramat, Keivan Etessam Yazdani
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Patent number: 7898056Abstract: Disclosed is a seal-ring architecture that can minimize noise injection from noisy digital circuits to sensitive analog and/or radio frequency (RF) circuits in system-on-a-chip (SoC) applications. In order to improve the isolation, the seal-ring structure contains cuts and ground connections to the segment which is close to the analog circuits. The cuts are such that the architecture is fully compatible with standard design rules and that the mechanical strength of the seal rings is not significantly sacrificed. Some embodiments also include a grounded p-tap ring between the analog circuits and the inner seal ring in order to improve isolation. Some embodiments also include a guard strip between the analog circuits and the digital circuits to minimize the noise injection through the substrate.Type: GrantFiled: December 9, 2008Date of Patent: March 1, 2011Assignee: Alvand Technology, Inc.Inventors: Mansour Keramat, Syed S. Islam, Mehrdad Heshami
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Patent number: 7852248Abstract: In one embodiment of the present invention, at least at one stage of a Sigma-Delta analog-to-digital converter (ADC) is disclosed to include means for receiving a voltage at least one of the inputs of an operational amplifier, the operational amplifier having at least one output coupled to the at least one of the inputs via an at least one integration capacitor, means for transforming the voltage to a current and means for integrating the current on the at least one of the integration capacitors, during integration time and varying the resistance of at least one of a variable resistors coupled to the operational amplifier during integration time.Type: GrantFiled: December 9, 2008Date of Patent: December 14, 2010Assignee: Alvand Technology, Inc.Inventors: Mansour Keramat, Ali Agah, Ali Tabatabaei
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Patent number: 7606546Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: April 18, 2008Date of Patent: October 20, 2009Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7558348Abstract: A radio frequency antenna system and high-speed digital data link are disclosed to, among other things, reduce electromagnetic interference (“EMI”) at relatively high data rates while reducing the manufacturing complexities associated with conventional data links. In one embodiment, a radio frequency (“RF”) antenna system includes an antenna and an RF radio coupled to the antenna for receiving wireless RF signals. In particular, the RF radio is configured to digitize RF signals at a fixed data rate to form digitized data signals and to apply the digitized data signals at a variable data rate to a high-speed digital link. The variable data rate distributes the signal energy of the digitized data signals over one or more bands of frequencies, thereby beneficially altering an EMI spectral profile describing emissions that develop as the digitized data signals are transported through a channel.Type: GrantFiled: May 18, 2005Date of Patent: July 7, 2009Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Mehrdad Heshami, Feng Bao, Timothy C. Kuo, Douglas J. Hogberg, Bo Liang, Edward Wai Yeung Liu
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Patent number: 7548740Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: December 12, 2007Date of Patent: June 16, 2009Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7542749Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: December 12, 2007Date of Patent: June 2, 2009Assignee: NVIDIA CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7499690Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: December 12, 2007Date of Patent: March 3, 2009Assignee: NVIDIA CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Patent number: 7473955Abstract: A fabricated cylinder capacitor having two or more layers is provided, each layer having a bottom plate and top plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor. The layers may comprise five metal layers and may be produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more cylinder capacitors where a set of connectors connect all top plates of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.Type: GrantFiled: March 7, 2006Date of Patent: January 6, 2009Assignee: Alvand Technologies, Inc.Inventors: Mehrdad Heshami, Mansour Keramat
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Patent number: 7456462Abstract: A layered capacitor having top and bottom plates formed from multiple layers. The capacitor has a bottom layer comprising a bottom plate portion and at least one upper layer, each upper layer comprising top and bottom plate portions. A first set of vias connect the bottom plate portions and a second set of vias connect the top plate portions. The bottom plate portions and the first set of vias comprise a U-shaped bottom plate and the top plate portions and the second set of vias comprise a top plate of the capacitor device. The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, which may be used in a SAR ADC.Type: GrantFiled: March 7, 2006Date of Patent: November 25, 2008Assignee: Alvand Technologies, Inc.Inventors: Mehrdad Heshami, Mansour Keramat
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Publication number: 20080273637Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: ApplicationFiled: July 15, 2008Publication date: November 6, 2008Applicant: NVIDIA CORPORATIONInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 7447490Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: GrantFiled: May 18, 2005Date of Patent: November 4, 2008Assignee: Nvidia CorporationInventors: Timothy C. Kuo, Mansour Keramat, Edward Wai Yeung Liu
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Patent number: 7446365Abstract: A fabricated layered capacitor having three layers is provided. The first bottom layer comprises a first bottom plate portion, the second middle layer comprises a first top plate portion, and the third top layer comprises a second bottom plate portion of the layered capacitor. A set of vias connects the first and second bottom plate portions. The top plate portion may extend past the bottom plate portions. The layered capacitor may have a different number of layers (e.g., five layers). The layers may comprise metal layers produced using semiconductor fabrication methods. Also provided is a capacitor array having two or more layered capacitors where connectors connect all top plate portions of the capacitors. The capacitor array may be used in a capacitive DAC, the capacitors being connected according to the architecture of the DAC. The capacitive DAC may be used in a SAR ADC.Type: GrantFiled: March 7, 2006Date of Patent: November 4, 2008Assignee: Alvand Technologies, Inc.Inventors: Mehrdad Heshami, Mansour Keramat
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Patent number: 7403150Abstract: An analog-to-digital converter architecture is described. An analog-to-digital converter circuit includes a switched capacitor circuit structure to receive an input voltage signal and one or more reference voltage signals. The analog-to-digital converter circuit also includes a comparator device array coupled to the switched capacitor circuit structure.Type: GrantFiled: September 20, 2006Date of Patent: July 22, 2008Assignee: Alvand Technologies, Inc.Inventors: Mehrdad Heshami, Mansour Keramat
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Patent number: 7389095Abstract: A system, method and system are disclosed for using a variable frequency clock generator to synchronize an average data rate over intervals of time in a variable clock domain to make it equal to a fixed data rate in a fixed clock domain while reducing electromagnetic interference, among other things. In various embodiments, setting the data rates equal to each other minimizes storage used to transition data signals between clock domains. In one embodiment, a variable frequency clock generator includes a phase modulator configured to form a variable frequency clock. Also, the variable clock generator is configured to maintain an average frequency over specific periods of time for the range of discrete frequencies. The phase-offset controller sets an average clock having substantially no offset between a fixed data rate in the fixed clock domain and an average data rate in the variable clock domain.Type: GrantFiled: May 18, 2005Date of Patent: June 17, 2008Assignee: Nvidia CorporationInventors: Tao Liu, Mansour Keramat, Edward Wai Yeung Liu, Mehrdad Heshami, Timothy C. Kuo
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Publication number: 20060264192Abstract: An apparatus for calibrating gain of an radio frequency receiver (“Rx”) is disclosed to provide, among other things, a structure for performing in-situ gain calibration of an RF integrated circuit over time and/or over temperature without removing the RF integrated circuit from its operational configuration, especially when the gain of the RF integrated circuit is susceptible to variations in process, such as inherent with the CMOS process. In one embodiment, an exemplary apparatus includes a thermal noise generator configured to generate thermal noise as a calibrating signal into an input of an Rx path of an RF integrated circuit. The apparatus also includes a calibrator configured to first measure an output signal from an output of the Rx path, and then adjust a gain of the Rx path based on the thermal noise. In one embodiment, the thermal noise generator further includes a termination resistance and/or impedance.Type: ApplicationFiled: May 18, 2005Publication date: November 23, 2006Inventors: Timothy Kuo, Mansour Keramat, Edward Liu