Patents by Inventor Manuel Antonio D'Abreu

Manuel Antonio D'Abreu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9177610
    Abstract: An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differential signaling interface.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 3, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
  • Patent number: 9177609
    Abstract: An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and periphery circuitry corresponding to the second memory core. The periphery die is responsive to a memory controller and configured to initiate a first memory operation at the first memory core and a second memory operation at the second memory core.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 3, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
  • Patent number: 9159426
    Abstract: A method includes forming a first group of memory cells coupled to a first conductive channel. The first conductive channel is substantially perpendicular relative to a surface of a substrate. The method further includes forming a second group of memory cells coupled to a second conductive channel. The second conductive channel is electrically coupled to the first conductive channel and is substantially perpendicular relative to the surface of the substrate.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: October 13, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventor: Manuel Antonio D'Abreu
  • Patent number: 9153331
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in a controller of the data storage device, a value of a particular write/erase (W/E) counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular W/E counter and that includes a storage element that is tracked by a particular cell erase counter of the set of counters. The method includes, in response to the value of the particular W/E counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory at least partially based on the value of the particular cell erase counter.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: October 6, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • Patent number: 9142261
    Abstract: An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a serializer/deserializer interface.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: September 22, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi
  • Patent number: 9141534
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to a read access to a particular region of the non-volatile memory that is tracked by the particular counter. Read accesses to a first region of the non-volatile memory are tracked by a first counter of the set of counters and read accesses to a second region of the non-volatile memory are tracked by a second counter of the set of counters. The method includes, in response to the value of the particular counter indicating that a count of read accesses to the particular region equals or exceeds a first threshold, initiating a remedial action to the particular region of the non-volatile memory.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: September 22, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala
  • Patent number: 9129689
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes comparing, in the controller, a count of erase pulses to an erase pulse threshold. The count of erase pulses corresponds to a particular region of the non-volatile memory. The method includes, in response to the count of erase pulse satisfying the erase pulse threshold, initiating a remedial action with respect to the particular region of the non-volatile memory.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 8, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • Publication number: 20150242270
    Abstract: A data storage device includes a memory including a group of storage elements. The memory is configured to read the group of the storage elements. A controller is coupled to the memory. The controller is configured to, in response to a first error correction code (ECC) procedure determining that a first plurality of bit values obtained using a first read voltage to read the group of storage elements is uncorrectable, instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values. The controller is further configured to compare the first plurality of bit values with the second plurality of bit values to identify a first set of bits having different values in the first plurality of bit values as compared to the second plurality of bit values and to change one or more values of the first plurality of bit values for one or more bits in the first set of bits to generate a first plurality of corrected bit values.
    Type: Application
    Filed: April 28, 2015
    Publication date: August 27, 2015
    Inventors: MANUEL ANTONIO D-ABREU, STEPHEN SKALA
  • Patent number: 9117533
    Abstract: A data storage device includes a memory and a controller and may perform a method that includes updating, in the controller, a value of a particular counter of a set of counters in response to an erase operation to a particular region of the non-volatile memory that is tracked by the particular counter. The method includes, in response to the value of the particular counter indicating that a count of erase operations to the particular region satisfies a first threshold, initiating a remedial action to the particular region of the non-volatile memory.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: August 25, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis, Stephen Skala
  • Patent number: 9110788
    Abstract: A storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method performed in the data storage device includes receiving, at the controller, first data and second data to be stored at the non-volatile memory. The method further includes sending, from the controller, the first data, the second data, and dummy data to the non-volatile memory to be stored at respective logical pages of a single physical page in the non-volatile memory. The single physical page includes multiple storage elements that are programmable into multiple voltage states according to a mapping of bits to states. The dummy data prevents a storage element of the single physical page from being programmed to a particular voltage state of the multiple voltage states.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: August 18, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Dimitris Pantelakis
  • Patent number: 9105333
    Abstract: A data storage device includes a memory die, where the memory die includes a NAND flash memory and a resistive random access memory (ReRAM). The memory die also includes an interface coupled to the ReRAM and the NAND flash memory. The interface is configured to support on-chip copying of data between the NAND flash memory and the ReRAM.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: August 11, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Xinde Hu, Sergey Anatolievich Gorobets, Manuel Antonio D'Abreu
  • Publication number: 20150178151
    Abstract: A data storage device includes a nonvolatile memory and a controller having a decoder. The nonvolatile memory is operatively coupled to the controller. The nonvolatile memory is configured to store a set of bits. The decoder is configured to receive the set of bits from the memory. The decoder is further configured to perform a decoding operation using the set of bits based on a parity check matrix. The parity check matrix includes a block row. The block row has a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix within the block row by at least a threshold number of null sub-matrices of the block row.
    Type: Application
    Filed: December 20, 2013
    Publication date: June 25, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: ZONGWANG LI, MANUEL ANTONIO D'ABREU
  • Publication number: 20150169406
    Abstract: A data storage device includes a buffer and a decoder. The buffer is configured to receive a set of bits representing data stored at a memory. The decoder is configured to receive the set of bits from the buffer. The decoder is further configured to perform a decoding operation based on the set of bits at a decoding throughput that corresponds to a storage size of the buffer.
    Type: Application
    Filed: December 16, 2013
    Publication date: June 18, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: ZONGWANG LI, MANUEL ANTONIO D'ABREU
  • Patent number: 9053790
    Abstract: A data storage device includes a resistive random access memory (ReRAM) having a three-dimensional (3D) memory configuration that is monolithically formed in one or more physical levels of arrays of memory cells having an active area disposed above a silicon substrate. The data storage device further includes circuitry associated with operation of the memory cells. A method includes performing a first number of write operations to the ReRAM. The method further includes incrementing a value of a counter a second number of times in response to performing at least one of the write operations. The second number is less than the first number.
    Type: Grant
    Filed: July 1, 2014
    Date of Patent: June 9, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Xinde Hu, Manuel Antonio D'Abreu
  • Publication number: 20150154111
    Abstract: A storage device includes non-volatile memory and a controller. A method performed in the data storage device includes sending an instruction to a host device to cause the host device to perform one or more specified computations. The method further includes receiving a response from the host device. The response is based on execution of the one or more specified computations.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 4, 2015
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: MANUEL ANTONIO D'ABREU, DIMITRIS C. PANTELAKIS
  • Patent number: 9047210
    Abstract: A data storage device includes a memory including a plurality of storage elements. The memory is configured to read a group of the storage elements using a first read voltage to obtain a first plurality of bit values. A controller is coupled to the memory. The controller is configured to initiate a first error correction code (ECC) procedure on the first plurality of bit values. In response to the first ECC procedure determining that the first plurality of bit values is not correctable, the controller is further configured to instruct the memory to read the group of the storage elements using a second read voltage to obtain a second plurality of bit values, and to change one or more values of the first plurality of bit values to corresponding values of the second plurality of bit values to generate a first plurality of corrected bit values.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: June 2, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Manuel Antonio D'Abreu, Stephen Skala
  • Patent number: 9042160
    Abstract: A method includes, in a data storage device that includes a non-volatile memory and a resistive random access memory (ReRAM) on the same die, receiving data from a memory controller via a bus. The method also includes routing the data to data latches of the non-volatile memory via a first path and to the ReRAM via a second path distinct from the first path.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 26, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventors: Sergey Anatolievich Gorobets, Aaron Keith Olbrich, Manuel Antonio D'Abreu, Xinde Hu
  • Patent number: 9036428
    Abstract: A method includes, at a non-volatile memory having a three dimensional (3D) memory configuration, performing an erase operation. Performing the erase operation includes providing a first control signal to isolate a first portion of a string of the non-volatile memory from a second portion of the string. Performing the erase operation further includes providing a first erase signal to erase the second portion of the string while data is maintained at the first portion of the string.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: May 19, 2015
    Assignee: SANDISK TECHNOLOGIES INC.
    Inventor: Manuel Antonio D'Abreu
  • Patent number: 9021343
    Abstract: A data storage device includes a non-volatile memory having a three-dimensional (3D) memory configuration. The data storage device may further include selection circuitry configured to select data for a parity operation in accordance with a parity scheme. The parity scheme may correspond to a string-based and group-based striping pattern.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: April 28, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Xinde Hu, Manuel Antonio D'Abreu
  • Patent number: 8996838
    Abstract: A data storage device includes a memory having a three-dimensional (3D) memory configuration. The memory includes a structure that extends through multiple layers of the memory. A method includes storing information at the data storage device. The information identifies a location associated with a variation of the structure. The method further includes accessing the information.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: March 31, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Manuel Antonio D'Abreu, Xinde Hu