Patents by Inventor Manzur Gill

Manzur Gill has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5740105
    Abstract: An EPROM or flash EEPROM, which has an array of single-transistor, stacked-gate, memory cells. Active areas for transistor elements are in columns up and down the array, with columns being isolated by thick field oxide strips (220). Word lines (236) and source lines (212) run across the array. Bit lines (216) run along the active area columns to connect transistor drains (218). Bit lines are perpendicular to word lines. Each stacked gate includes a control gate (232) and a floating gate (230), with the latter having a top portion (230b) and a bottom portion (230a) that are separately deposited and etched. The bottom portion (230a) is etched in strips along the active area columns, and define the gate width of each cell. The top portion (230b) overlaps the bottom portion (230a) to improve capacitance between control gate (232) and floating gate (230).
    Type: Grant
    Filed: October 17, 1996
    Date of Patent: April 14, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill
  • Patent number: 5661060
    Abstract: A Flash EEPROM memory array and method for making the same is provided. The memory array has rectangularly shaped field oxide regions. A field oxide layer is grown on a substrate having p-wells. The field oxide layer is selectively etched to provide the resulting field oxide regions. Subsequent method steps provide tunnel oxide regions, floating gates oxide-nitride-oxide layers, bit lines, oxide spacers and word lines, word line to metal dielectric, contacts, metal and passivation.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: August 26, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Manzur Gill, Etan Shacham
  • Patent number: 5570314
    Abstract: An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A layer of field oxide is grown over an n-type substrate having a p-well and the layer of field oxide is selectively etched to form rows of field oxide. Rows of tunnel oxide are formed between the rows of field oxide. A first layer of polysilicon, or poly-1, is formed over the wafer and a layer of ONO is formed over the poly-1. Using the same mask, the ONO, poly-1, field oxide, and tunnel oxide are stack etched. Bit lines are formed, followed by oxide spacers. A second layer of polysilicon, or poly-2 is formed and selectively etched to form word lines. The exposed ONO and poly-1 are etched using the same mask to form floating gate regions. Subsequent process steps provide word lines to metal dielectric, contacts, metal and passivation.
    Type: Grant
    Filed: December 28, 1994
    Date of Patent: October 29, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Manzur Gill
  • Patent number: 5565371
    Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (21). Each memory cell includes a source region (11) and a drain region (12) formed in a shared drain-column line (19), with a corresponding channel region in between. A Fowler-Nordheim tunnel-window (13a) is located opposite the channel over the source-column line (17) connected to source (11). A floating-gate conductor (13) includes a channel section (29) and a tunnel-window section (28). The floating-gate conductor is formed in two stages, the first stage forming the channel section (29) and the tunnel-window section (28) from a first-level polysilicon. This floating-gate channel section (29) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (29).
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: October 15, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill
  • Patent number: 5550772
    Abstract: A non-volatile memory system is disclosed which includes an array of multi-state N channel floating gate memory cells along with associated control circuitry for programming, reading and erasing the cells of the array. Small geometry single transistor memory cells are used which are capable of operating both in the enhancement and the depletion modes of operation. The associated control circuitry includes circuitry for programming selected cells of the array to one of a multiplicity of programmed states, typically four states. At least one of the programmed states results in the cell having a negative threshold voltage, relative to the source region of the cell, thereby indicating depletion mode operation, with the remaining states resulting in the cell having positive threshold voltage. The use of both polarity threshold voltages increases the voltage margin between states thereby enhancing the reliability of read/write operations.
    Type: Grant
    Filed: February 13, 1995
    Date of Patent: August 27, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Manzur Gill
  • Patent number: 5537362
    Abstract: A Low-voltage Electrically Erasable, Electrically Programmable Read Only Memory (EEPROM) and a method for reading memory cells in the EEPROM. During a read operation address input is provided to an address latch and edge detector, which supplies a changed address signal to a charge-sharing word line voltage generator, supplies word line address signals to a word line address decoder, and supplies bit line address signals to a bit line address decoder and sense amplifier circuit. The word line address decoder provides a positive voltage from a positive voltage source to a selected word line in the memory array and provides a voltage that is negative with respect to ground to deselected word lines. The bit line address decoder and sense amplifier circuit grounds selected source bit lines and senses drain to source current to read the memory cells.
    Type: Grant
    Filed: December 6, 1994
    Date of Patent: July 16, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Manzur Gill, Vincent Fong
  • Patent number: 5523249
    Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch).
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: June 4, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, David J. McElroy, Sung-Wei Lin, Inn K. Lee
  • Patent number: 5521110
    Abstract: An EEPROM and method for making the same, having precisely shaped field oxide regions and memory cells, to provide improved electrical operating characteristics and increased memory density. A layer of field oxide is grown over an n-type substrate having a p-well and the layer of field oxide is selectively etched to form rows of field oxide. Rows of tunnel oxide are formed between the rows of field oxide. A first layer of polysilicon, or poly-1, is formed over the wafer and a layer of ONO is formed over the poly-1. Using the same mask, the ONO, poly-1, field oxide, and tunnel oxide are stack etched. Bit lines are formed, followed by oxide spacers. A second layer of polysilicon,or poly-2 is formed and selectively etched to form word lines. The exposed ONO and poly-1 are etched using the same mask to form floating gate regions. Subsequent process steps provide word lines to metal dielectric, contacts, metal and passivation.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: May 28, 1996
    Assignee: National Semiconductor Corporation
    Inventor: Manzur Gill
  • Patent number: 5469383
    Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
    Type: Grant
    Filed: June 24, 1994
    Date of Patent: November 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Dave J. McElroy, Manzur Gill, Pradeep L. Shah
  • Patent number: 5420060
    Abstract: A contact-free floating-gate non-volatile memory cell array and process with silicided NSAG bitlines and with source/drain regions buried beneath relatively thick silicon oxide. The bitlines have a relatively small resistance, eliminating the need for parallel metallic conductors with numerous bitline contacts. The array has relatively small bitline capacitance and may be constructed having relatively small dimensions. Isolation between bitlines is by thick field oxide. Wordlines may be formed from silicided polycrystalline or other material with low resistivity. Coupling of programming and erasing voltages to the floating gate is improved by extending the gates over the thick field oxide and perhaps by using an insulator with relatively high dielectric constant between the control gate and the floating gate. The sides of the floating gates are defined with a single patterning step. The resulting structure is a dense cross-point array of programmable memory cells.
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, Howard L. Tigelaar
  • Patent number: 5418741
    Abstract: A memory cell array for a nonvolatile memory device having single-transistor cells (10). Row lines (15) connect the control gates of each row of cells. Column lines (17) connect the drain regions (11) and source regions (12) of columns of cells, such that pairs of row-adjacent cells share a column line (17). Each shared column line (17) has two junctions for each pair of cells that share the column line. One junction is graded for source regions (12) and the other is abrupt for drain regions (11).
    Type: Grant
    Filed: January 6, 1994
    Date of Patent: May 23, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill
  • Patent number: 5371031
    Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source region (11) and a drain region (12), with a corresponding channel region between. A Fowler-Nordheim tunnel-window (13a) is located over the source line (17) connected to source (11). The source line (17) consists of alternating buried N+ windows (17a) and source regions (11). A floating gate (13) includes a tunnel-window section. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the source (11) and drain (12) regions, such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch).
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: December 6, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, Inn K. Lee
  • Patent number: 5365082
    Abstract: A CMOS memory cell array, and a process for making it, that avoids problems caused by LOCOS isolation of cells. Moats are formed by etching away columns of a thick field oxide layer. The moats have two-tiered sidewalls, such that an upper tier is sloped, and a lower tier is more vertical. This approach provides the advantages of sloped sidewalls, but avoids filament problems. After the moats are formed, subsequent fabrication steps may be in accordance with conventional fabrication techniques for CMOS arrays.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: November 15, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, Pradeep L. Shah, Dave J. McElroy
  • Patent number: 5354703
    Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).
    Type: Grant
    Filed: June 29, 1993
    Date of Patent: October 11, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill
  • Patent number: 5350706
    Abstract: A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.
    Type: Grant
    Filed: September 30, 1992
    Date of Patent: September 27, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Dave J. McElroy, Manzur Gill, Pradeep L. Shah
  • Patent number: 5340768
    Abstract: The structure and method of this invention provide, for example, electrical isolation between active elements in adjacent rows and/or columns of an integrated circuit by use of a self-aligned field-plate conductor formed over and insulated from the substrate regions that are bounded by the channel regions of field-effect transistors in adjacent rows and that are bounded by the bitlines forming those transistors in a column. The field-plate conductor is formed, for example, in a strip that extends over the isolation areas and thermal insulator regions between row lines of the memory cell array. The field-plate conductor strip is connected to a voltage supply that has a potential with respect to the potential of the semiconductor substrate which causes the isolation areas to be nonconductive. Component density may be increased over that of prior-art structures and methods.
    Type: Grant
    Filed: May 28, 1993
    Date of Patent: August 23, 1994
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill
  • Patent number: 5334550
    Abstract: An integrated circuit structure and process relating to a self-aligned window at the recessed junction of two insulating regions formed on the surface of a semiconductor body. The window may include a trench forming an isolation region between doped semiconductor regions, or may include an electrical conductor connected to a doped semiconductor region, or may include an electrical conductor separated from doped semiconductor regions by an electrical insulator. Embodiments include, but are not limited to, a field-effect transistor, a tunnelling area for a floating gate transistor, and an electrical connection to a doped area of the substrate.
    Type: Grant
    Filed: January 15, 1993
    Date of Patent: August 2, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: David J. McElroy, Sung-Wei Lin, Manzur Gill
  • Patent number: 5321288
    Abstract: A nonvolatile memory cell having separate regions for programming and erasing. The cells are formed in an array at a face of a semiconductor body, each cell including a source that is part of a source-column line and including a drain that is part of a drain-column line. Each cell has first and second sub-channels between source and drain. The conductivity of the first sub-channel of each cell is controlled by a field-plate, which is part of a field-plate-column line, positioned over and insulated from the first sub-channel. The conductivity of each of the second sub-channels is controlled by a floating gate formed over and insulated from the second sub-channel. Each floating gate has a first tunnelling window positioned over the adjacent source-column line and has a second tunnelling window positioned over the adjacent drain-column line. Row lines, including control gates, are positioned above and insulated from the floating gates of the cells for reading, programming and erasing the cells.
    Type: Grant
    Filed: June 29, 1992
    Date of Patent: June 14, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Manzur Gill, Theodore D. Lindgren
  • Patent number: 5313432
    Abstract: A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
    Type: Grant
    Filed: November 12, 1991
    Date of Patent: May 17, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Sung-Wei Lin, John F. Schreck, Phat C. Truong, David J. McElroy, Harvey J. Stiegler, Benjamin H. Ashmore, Jr., Manzur Gill
  • Patent number: RE35356
    Abstract: An electrically-erasable, electrically-programmable, read-only-memory cell array is formed in pairs at a face of a semiconductor substrate (22). Each memory cell includes a source (11) and a drain (12), with a corresponding channel (Ch) between. A control gate (14) is disposed over the floating gate (13), insulated by an intervening inter-level dielectric (27). The floating gate (13) and the control gate (14) include a channel section (Ch). The channel section (Ch) is used as a self-alignment implant mask for the sources (11) and drains (12), such that the channel-junction edges are aligned with the corresponding edges of the channel section (Ch). Each memory cell is programmed by hot-carrier injection from the channel to the floating gate (13), and erased by Fowler-Nordheim tunneling from the floating gate (13) to the source (11).
    Type: Grant
    Filed: March 17, 1995
    Date of Patent: October 22, 1996
    Assignee: Texas Instruments Incorporated
    Inventor: Manzur Gill