Patents by Inventor Marc A. Bergendahl
Marc A. Bergendahl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240112965Abstract: A semiconductor device includes a substrate, which further includes a cavity and a trench extended from the cavity. The semiconductor includes a first chip and a second chip on the substrate, a bridge chip interconnecting between the first and second chips and residing in the cavity, and underfill material filling the cavity and the trench, and surrounding the bridge chip.Type: ApplicationFiled: October 3, 2022Publication date: April 4, 2024Inventors: Chinami Marushima, Toyohiro Aoki, Takashi Hisada, Marc A. Bergendahl
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Publication number: 20240088268Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: ApplicationFiled: April 12, 2023Publication date: March 14, 2024Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 11876023Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.Type: GrantFiled: December 17, 2021Date of Patent: January 16, 2024Assignee: International Business Machines CorporationInventors: Marc A. Bergendahl, Christopher J. Penny, James John Demarest, Jean Wynne, Christopher J. Waskiewicz, Jonathan Fry
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Publication number: 20230352480Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.Type: ApplicationFiled: December 1, 2022Publication date: November 2, 2023Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 11791270Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: GrantFiled: May 10, 2021Date of Patent: October 17, 2023Assignee: International Business Machines CorporationInventors: Kamal K Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, Ravi K. Bonam, Hiroyuki Mori, Yang Liu, Paul S. Andry, Isabel De Sousa
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Patent number: 11776957Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.Type: GrantFiled: December 7, 2022Date of Patent: October 3, 2023Assignee: TESSERA LLCInventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
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Publication number: 20230282641Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.Type: ApplicationFiled: December 7, 2022Publication date: September 7, 2023Inventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
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Patent number: 11688632Abstract: Semiconductor devices and methods for forming semiconductor devices include opening at least one contact via through a sacrificial material down to contacts. Sides of the at least one contact via are lined by selectively depositing a barrier on the sacrificial material, the barrier extending along sidewalls of the at least one contact via from a top surface of the sacrificial material down to a bottom surface of the sacrificial material proximal to the contacts such that the contacts remain exposed. A conductive material is deposited in the at least one contact via down to the contacts to form stacked contacts having the hard mask on sides thereof. The sacrificial material is removed.Type: GrantFiled: December 29, 2020Date of Patent: June 27, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alex Joseph Varghese, Marc A. Bergendahl, Andrew M. Greene, Dallas Lea, Matthew T. Shoudy, Yann Mignot, Ekmini A. De Silva, Gangadhara Raja Muthinti
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Publication number: 20230197531Abstract: Embodiments of the invention provide a method that includes forming an IC layer having an inactive region and an active region. The active region includes a device-under-fabrication (DUF). The inactive region includes a geometric feature having a geometric shape. A film is deposited over the active DUF and the geometric feature such that a first portion of the film will be part of the active DUF, and such that a second portion of the film is over the geometric feature. A geometric shape of the film over the geometric feature matches the geometric shape of the geometric feature. Determining a thickness of the film is based at least in part a difference between a footprint of the geometric shape of the film and a footprint of the geometric shape of the geometric feature.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: Marc A. Bergendahl, Christopher J. Penny, James John Demarest, Jean Wynne, Christopher J. Waskiewicz, Jonathan Fry
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Patent number: 11673766Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.Type: GrantFiled: October 29, 2018Date of Patent: June 13, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gauri Karve, Tara Astigarraga, Eric Miller, Kangguo Cheng, Fee Li Lie, Sean Teehan, Marc Bergendahl
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Publication number: 20230178544Abstract: A CFET (complementary field effect transistor) structure including a substrate, a first CFET formed above the substrate, and a second CFET formed above the substrate. Each CFET includes a top FET and a bottom FET. Each of the top FET and bottom FET includes at least one nanosheet channel. The top FET of each CFET has a first polarity. The bottom FET of each a CFET comprises a second polarity. The top FET of the first CFET includes a first work function metal, and the top FET of the second CFET includes a second work function metal.Type: ApplicationFiled: December 6, 2021Publication date: June 8, 2023Inventors: Julien Frougier, Nicolas Loubet, Ruilong Xie, Marc A. Bergendahl, Joshua M. Rubin
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Publication number: 20230171114Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.Type: ApplicationFiled: November 30, 2021Publication date: June 1, 2023Inventors: Dallas Lea, Yann Mignot, Marc A. Bergendahl, Alex Joseph Varghese, Sean Teehan, Andrew M. Greene, Matthew T. Shoudy
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Patent number: 11652161Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.Type: GrantFiled: June 11, 2021Date of Patent: May 16, 2023Assignee: Tessera LLCInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 11646235Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.Type: GrantFiled: July 22, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Eric Miller, Marc A. Bergendahl, Kangguo Cheng, Sean Teehan, John Sporre
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Patent number: 11615992Abstract: A method of forming vertical transport field effect transistor (VTFET) devices is provided. The method includes forming a plurality of vertical fins on an upper insulating layer of a dual insulator layer semiconductor-on-insulator (SeOI) substrate, and forming two masking blocks on the plurality of vertical fins, wherein a portion of a protective layer and a fin template on each of the plurality of vertical fins is exposed between the two masking blocks. The method further includes removing a portion of the upper insulating layer between the two masking blocks to form a first cavity beneath the plurality of vertical fins, and forming a first bottom source/drain in the first cavity below the plurality of vertical fins. The method further includes replacing the two masking blocks with a masking layer patterned to have two mask openings above portions of the upper insulating layer adjacent to the first bottom source/drain.Type: GrantFiled: January 15, 2020Date of Patent: March 28, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Eric Miller, Marc A. Bergendahl, Kangguo Cheng, John Sporre, Gauri Karve, Fee Li Lie
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Patent number: 11557589Abstract: A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.Type: GrantFiled: March 30, 2020Date of Patent: January 17, 2023Assignee: Tessera, LLCInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
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Patent number: 11552077Abstract: A method of forming a power rail to semiconductor devices comprising removing a portion of the gate structure forming a gate cut trench separating a first active region of fin structures from a second active region of fin structures. A conformal etch stop layer is formed in the gate cut trench. A fill material is formed on the conformal etch stop layer filling at least a portion of the gate cut trench. The fill material has a composition that is etched selectively to the conformal etch stop layer. A power rail is formed in the gate cut trench. The conformal etch stop layer obstructs lateral etching during forming the power rail to substantially eliminate power rail to gate structure shorting.Type: GrantFiled: April 2, 2021Date of Patent: January 10, 2023Assignee: TESSERA LLCInventors: Marc A. Bergendahl, Andrew M. Greene, Rajasekhar Venigalla
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Publication number: 20220359401Abstract: A direct bonded heterogeneous integration (DBHi) device includes a substrate including a trench formed in a top surface of the substrate. The DBHi device further includes a first chip coupled to the substrate on a first side of the trench by a plurality of first interconnects. The DBHi device further includes a second chip coupled to the substrate on a second side of the trench by a plurality of second interconnects. The second side of the trench is arranged opposite the first side of the trench. The DBHi device further includes a bridge coupled to the first chip and to the second chip by a plurality of third interconnects such that the bridge is suspended in the trench. The DBHi device further includes a non-conductive paste material surrounding the plurality of third interconnects to further couple the bridge to the first chip and to the second chip.Type: ApplicationFiled: May 10, 2021Publication date: November 10, 2022Inventors: Kamal K. Sikka, Maryse Cournoyer, Pascale Gagnon, Charles C. Bureau, Catherine Dufort, Dale Curtis McHerron, Vijayeshwar Das Khanna, Marc A. Bergendahl, Dishit Paresh Parekh, RAVI K. BONAM, HIROYUKI MORI, Yang Liu, Paul S. Andry, Isabel De Sousa
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Patent number: 11462631Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.Type: GrantFiled: April 14, 2020Date of Patent: October 4, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Eric Miller, Fee Li Lie, Gauri Karve, Marc A. Bergendahl, John Ryan Sporre
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Patent number: 11362194Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device on an integrated circuit (IC). The method includes forming a containment structure having a non-sacrificial fin-containment region and a sacrificial fin-containment region, wherein the containment structure is configured to define a source or drain (S/D) cavity. A S/D region is formed in the S/D cavity. The S/D region includes a contained S/D region defined by the containment structure. The S/D region further includes a non-contained S/D region positioned above the containment structure. The IC is exposed to an etchant that is selective to the sacrificial fin-containment region, non-selective to the non-sacrificial fin-containment region, and non-selective to a plurality of spacers on the IC. Exposing the IC to the etchant selectively removes the sacrificial fin-containment region and exposes sidewalls of the contained S/D region.Type: GrantFiled: January 22, 2020Date of Patent: June 14, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alexander Reznicek, Ruilong Xie, Kangguo Cheng, Marc A. Bergendahl