Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured receive data streams from multiple different host systems and keep data for the separate streams in separate sub-drives. The method may include dynamically changing overprovisioning of the sub-drives in response to changes in relative workload measurements of data writes coming from the different host systems.

Abstract: A system and method is disclosed for managing data in a non-volatile memory. The system may include a non-volatile memory having multiple non-volatile memory sub-drives. A controller of the memory system is configured receive data streams from multiple different host systems and keep data for the separate streams in separate sub-drives. The method may include dynamically changing overprovisioning of the sub-drives in response to changes in relative workload measurements of data writes coming from the different host systems.

Abstract: An integrated I/O controller in an integrated circuit is provided for centralized data management. The integrated circuit includes a host interface, a disk interface, and a mapping controller implemented in hardware to speed data processing and provide fault tolerance as exemplified with RAID configurations. The mapping controller provides block mapping across a plurality of peripherals or disk drives in a disk array. The integrated I/O controller can be utilized in storage area network systems and network area storage systems as well as other networking systems or devices.

Abstract: An integrated I/O controller in an integrated circuit is provided for centralized data management. The integrated circuit includes a host interface, a disk interface, and a mapping controller implemented in hardware to speed data processing and provide fault tolerance as exemplified with RAID configurations. The mapping controller provides block mapping across a plurality of peripherals or disk drives in a disk array. The integrated I/O controller can be utilized in storage area network systems and network area storage systems as well as other networking systems or devices.

Abstract: An intelligent disk drive employing a controller which performs high speed error correction and miscorrection detection using a finite field processor. The error correction code is defined over a finite field and the error detection code is defined over an extension field of the finite field. The finite field processor performs calculation over both the finite field and extension field to provide high speed error correction and correction validation.

Abstract: An intelligent disk drive includes a controller which embeds user data address information into error correction code check symbols written to the data storage disk. The address information is not written to disk, but address errors are detected by decoding the error correction code check symbols during read operations. Disk space is saved while maintaining robust address error detection.

Abstract: Access to a buffer memory is provided by a controller architecture and method employing an arbiter state machine for control of data transfer between multiple external peripheral devices and the dynamic random access memory buffer. Data transfer channels for each peripheral device include a first-in, first-out sub-buffer. Each data transfer channel communicates transfer requests to the arbiter when data is present in the FIFO. When data transfer to or from the FIFO nears an overrun or underrun condition, the data channel issues an urgent request to the arbiter state machine. The arbiter state machine prioritizes data transfer requests for enabling transfer between the buffer memory and data channels. Once a data transfer is in process it continues uninterrupted unless an urgent request is received from another device. In addition, the invention includes a refresh circuit for the dynamic RAM incorporating similar request and urgent request signals provided to the arbiter state machine for resolution.