Patents by Inventor Marc Tarabbia
Marc Tarabbia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220367360Abstract: A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.Type: ApplicationFiled: August 2, 2022Publication date: November 17, 2022Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 11444031Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.Type: GrantFiled: September 30, 2020Date of Patent: September 13, 2022Assignee: GLOBALFOUNDRIES U.S. INC.Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20210013150Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers.Type: ApplicationFiled: September 30, 2020Publication date: January 14, 2021Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 10833018Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.Type: GrantFiled: July 3, 2019Date of Patent: November 10, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20190326219Abstract: A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.Type: ApplicationFiled: July 3, 2019Publication date: October 24, 2019Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Publication number: 20160268204Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.Type: ApplicationFiled: May 25, 2016Publication date: September 15, 2016Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 9355910Abstract: A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.Type: GrantFiled: December 13, 2011Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES, INC.Inventors: Mahbub Rashed, Irene Y. Lin, Steven Soss, Jeff Kim, Chinh Nguyen, Marc Tarabbia, Scott Johnson, Subramani Kengeri, Suresh Venkatesan
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Patent number: 9177963Abstract: Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.Type: GrantFiled: November 18, 2013Date of Patent: November 3, 2015Assignee: GLOBALFOUNDRIES INC.Inventors: Anurag Mittal, Marc Tarabbia
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Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
Patent number: 9087706Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.Type: GrantFiled: December 23, 2014Date of Patent: July 21, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia -
Patent number: 9059093Abstract: Methods for forming a variable fin FinFET cell wherein a plurality of fins is formed above a substrate, a portion of a fin is removed, forming a fin tip, a first area of a gate oxide layer is formed above the fin tip, and a second area of the gate oxide layer is formed above at least a remaining portion of the plurality of fins, wherein the first area is thicker than the second area.Type: GrantFiled: November 15, 2013Date of Patent: June 16, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Marc Tarabbia, Anurag Mittal, Nader Hindawy
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Publication number: 20150137203Abstract: Methods for forming a variable fin FinFET cell that can withstand a larger voltage without gate oxide breakdown at a fin tip and the resulting devices are disclosed. A plurality of fins is formed above a substrate, a portion of a fin is removed, forming a fin tip, a first area of a gate oxide layer is formed above the fin tip, and a second area of the gate oxide layer is formed above at least a remaining portion of the plurality of fins, wherein the first area is thicker than the second area.Type: ApplicationFiled: November 15, 2013Publication date: May 21, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Marc TARABBIA, Anurag MITTAL, Nader HINDAWY
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Publication number: 20150137258Abstract: Methods for a low voltage antifuse device and the resulting devices are disclosed. Embodiments may include forming a plurality of fins above a substrate, removing a portion of a fin, forming a fin tip, forming a first area of a gate oxide layer above at least the fin tip, forming a second area of the gate oxide layer above a remaining portion of the plurality of fins, wherein the first area is thinner than the second area, and forming a gate over at least the fin tip to form an antifuse one-time programmable device.Type: ApplicationFiled: November 18, 2013Publication date: May 21, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Anurag MITTAL, Marc TARABBIA
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Patent number: 9026977Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.Type: GrantFiled: August 16, 2013Date of Patent: May 5, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Marc Tarabbia, Norman Chen, Jian Liu, Nader Magdy Hindawy, Tuhin Guha Neogi, Mahbub Rashed, Anurag Mittal
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METHODS OF FORMING BIPOLAR DEVICES AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH BIPOLAR DEVICES
Publication number: 20150108580Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.Type: ApplicationFiled: December 23, 2014Publication date: April 23, 2015Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia -
Patent number: 8987128Abstract: An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.Type: GrantFiled: July 30, 2012Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Mahbub Rashed, Marc Tarabbia, Chinh Nguyen, David Doman, Juhan Kim, Xiang Qi, Suresh Venkatesan
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Patent number: 8987816Abstract: A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.Type: GrantFiled: October 21, 2014Date of Patent: March 24, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Jason Stephens, Marc Tarabbia, Nader Hindawy, Roderick Augur
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Methods of forming bipolar devices and an integrated circuit product containing such bipolar devices
Patent number: 8975130Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.Type: GrantFiled: June 28, 2013Date of Patent: March 10, 2015Assignee: GLOBALFOUNDRIES Inc.Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia -
Publication number: 20150052494Abstract: A method includes electrically connecting a plurality of cells of a standard cell library to a power rail. A contact area is deposited to connect a first active area and a second active area of a cell of a plurality cells. The first area and the second area are located on opposite sides of the rail and electrically connected to different drains. The contact area is electrically connected to the power rail using a via. The contact area is masked to remove a portion of the contact area to electrically separate the first active are from the second active area.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: GLOBALFOUNDRIES Inc.Inventors: Marc TARABBIA, Norman CHEN, Jian LIU, Nader Magdy HINDAWY, Tuhin Guha NEOGI, Mahbub RASHED, Anurag MITTAL
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Publication number: 20150035052Abstract: A method for forming CA power rails using a three mask decomposition process and the resulting device are provided. Embodiments include forming a horizontal diffusion CA power rail in an active layer of a semiconductor substrate using a first color mask; forming a plurality of vertical CAs in the active layer using second and third color masks, the vertical CAs connecting the CA power rail to at least one diffusion region on the semiconductor substrate, spaced from the CA power rail, wherein each pair of CAs formed by one of the second and third color masks are separated by at least two pitches.Type: ApplicationFiled: October 21, 2014Publication date: February 5, 2015Inventors: Jason STEPHENS, Marc TARABBIA, Nader HINDAWY, Roderick AUGUR
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METHODS OF FORMING BIPOLAR DEVICES AND AN INTEGRATED CIRCUIT PRODUCT CONTAINING SUCH BIPOLAR DEVICES
Publication number: 20150001634Abstract: One method disclosed herein includes performing at least one common process operation to form a plurality of first gate structures for each of a plurality of field effect transistors and a plurality of second gate structures above a region where a bipolar transistor will be formed and performing an ion implantation process and a heating process to form a continuous doped emitter region that extends under all of the second gate structures. A device disclosed herein includes a first plurality of field effect transistors with first gate structures, a bipolar transistor that has an emitter region and a plurality of second gate structures positioned above the emitter region, wherein the bipolar transistor comprises a continuous doped emitter region that extends laterally under all of the plurality of second gate structures.Type: ApplicationFiled: June 28, 2013Publication date: January 1, 2015Inventors: Jerome Ciavatti, Roderick Miller, Marc Tarabbia