Patents by Inventor Marcelino Dignum

Marcelino Dignum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180167329
    Abstract: In accordance with an embodiment, described herein is a system and method for providing a programmable packet classification framework for use in a network device in a high performance network. The packet classification framework can comprise a plurality of hardware-based programmable classification primitives, including a key composition primitive, a key composition rule primitive, a match action logical structure, and a next action primitive. The classification primitives can be logically strung together, with the results from one classification primitive fed into the next one until the processing of a data packet is completed. The classification framework can use a state machine to track states of the data packet processing, and dynamically adjust behaviors of the classification primitives based on the processing states of a data packet.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: ARVIND SRINIVASAN, MARCELINO DIGNUM
  • Publication number: 20180167318
    Abstract: In accordance with an embodiment, described herein is a system and method for partitioning classification resources in a network device in a high performance network. Classification resources can be configured into a plurality of levels of partitions, with one or more hardware-based partitions configured to store flow entries associated with frequently-used or performance-sensitive flows, and a firmware-based partition to access large lookup tables stored in one or more additional memories for classification resource scalability. A lookup key can be used for search for a flow entry match in the hardware-based partitions first. If there is a miss, the lookup key can be presented to the firmware-based partition for further search. Results from the firmware-based level can be dispatched back to a hardware-based parser for further processing. Flow entries can be moved between lookup tables by a partition management block based on utilization of the flow entries.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 14, 2018
    Inventors: ARVIND SRINIVASAN, MARCELINO DIGNUM
  • Patent number: 9544232
    Abstract: A system and method can support dynamic provisioning in a network switch environment, such as supporting virtualized switch classification tables in a network switch. The system can provide a plurality of memory blocks that can be used to build one or more classification tables for supporting packet processing. Furthermore, the system can comprise a management entity that operates to monitor traffic profile associated with a network port in the network switch. Then, the management entity can allocate one or more memory blocks in the plurality of memory blocks for a logical classification table, and associate the logical classification table with the network port.
    Type: Grant
    Filed: November 5, 2013
    Date of Patent: January 10, 2017
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Arvind Srinivasan, Marcelino Dignum
  • Publication number: 20150124813
    Abstract: A system and method can support dynamic provisioning in a network switch environment, such as supporting virtualized switch clasification tables in a network switch. The system can provide a plurality of memory blocks that can be used to build one or more classification tables for supporting packet processing. Furthermore, the system can comprise a management entity that operates to monitor traffic profile associated with a network port in the network switch. Then, the management entity can allocate one or more memory blocks in the plurality of memory blocks for a logical classification table, and associate the logical classification table with the network port.
    Type: Application
    Filed: November 5, 2013
    Publication date: May 7, 2015
    Applicant: Oracle International Corporation
    Inventors: Arvind Srinivasan, Marcelino Dignum
  • Publication number: 20070113171
    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), one or more hardware XML parser units, one or more cryptographic units and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or may be parsed in segments (e.g., as it is received). A parser unit parses a document or segment character by character, validates characters, assembles tokens from the document, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Jochen Behrens, Marcelino Dignum, Wayne Seltzer, William Zaumen, John Petry, Santiago Pericas-Geertsen, Biswadeep Nag
  • Publication number: 20070113170
    Abstract: A hardware finite state machine for facilitating the processing of an XML (Extensible Markup Language) document or other structured data stream. An accelerator is implemented in hardware to enable fast processing of a document (or a segment thereof). The accelerator includes a finite state machine that embodies a ternary CAM (Content-Addressable Memory) and associated RAM (Random Access Memory). Processing of the document is divided into multiple states, with each state transition defined by a markup delimiter that triggers the transition. The CAM is programmed with entries containing the processing states and, for each possible transition from that state, a pattern for matching delimiters that trigger the possible transitions. For a CAM entry matching the current processing state and a sequence of characters from the document, which may contain a delimiter, the associated RAM identifies the next state and any action to be taken (e.g., to shift the sequence of characters).
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Marcelino Dignum, Jochen Behrens, Wayne Seltzer
  • Publication number: 20070113222
    Abstract: A hardware unit for parsing an XML document includes embedded logic or circuitry for accessing the document, decoding it to change a character set, validating individual characters of the document, extracting tokens, maintaining a symbol table and generating binary token headers to describe the document's structure and convey the document's data to an application. Tokenization, the process of identifying tokens and generating token headers, may be controlled by a finite state machine that recognizes XML delimiters in the document's markup and activates state transitions based on the current state and the recognized delimiter. The parser unit may be implemented within a hardware XML accelerator that includes a processor, a DMA engine, a cryptographic engine, memory (e.g., for storing a document, maintaining a symbol table) and various interfaces (e.g., network, memory, bus).
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Marcelino Dignum, Jochen Behrens, Wayne Seltzer, William Zaumen
  • Publication number: 20070113172
    Abstract: A method and apparatus for performing virtualized parsing of an XML document. A document is divided into multiple segments, which may correspond to separate packets containing portions of the document, disk blocks, memory pages, etc. For each segment, a processor operating within an XML accelerator initiates parsing by identifying to a hardware parsing unit the document segment, a symbol table for the document and a location for storing state information regarding the parsing. Each segment is parsed in sequence, and the state information of the parsing is stored after each segment is completed, for retrieval when the next segment is to be parsed.
    Type: Application
    Filed: November 14, 2005
    Publication date: May 17, 2007
    Inventors: Jochen Behrens, Marcelino Dignum, Wayne Seltzer, William Zaumen