Patents by Inventor Marek Hytha

Marek Hytha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200161425
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween, and forming a gate on the channel region. The method may further include forming a body contact in the semiconductor layer and including a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Publication number: 20200161427
    Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS
  • Publication number: 20200161426
    Abstract: A semiconductor device may include a semiconductor layer and at least one contact in the semiconductor layer. The contact may include at least one oxygen monolayer constrained within a crystal lattice of adjacent semiconductor portions of the semiconductor layer and spaced apart from a surface of the semiconductor layer by between one and four monolayers, and a metal layer on the surface of the semiconductor layer above the at least one oxygen monolayer. The semiconductor portion between the oxygen monolayer and the metal layer may have a dopant concentration of 1×1021 atoms/cm3 or greater.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: DANIEL CONNELLY, Marek Hytha, Hideki Takeuchi, Richard Burton, Robert J. Mears
  • Publication number: 20200161429
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, DANIEL CONNELLY, MAREK HYTHA, RICHARD BURTON, ROBERT J. MEARS
  • Publication number: 20200161428
    Abstract: A method for making a FINFET may include forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice, with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a gate on the channel region.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Publication number: 20200161430
    Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and a gate on the channel region. The semiconductor device may further include a body contact in the semiconductor layer and comprising a body contact dopant diffusion blocking superlattice extending through the body contact to divide the body contact into a first body contact region and an second body contact region with the second body contact region having a same conductivity and higher dopant concentration than the first body contact region. The body contact dopant diffusion blocking superlattice may include a respective plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: November 16, 2018
    Publication date: May 21, 2020
    Inventors: HIDEKI TAKEUCHI, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Publication number: 20200135489
    Abstract: A method for making a semiconductor device may include forming a superlattice layer and an adjacent semiconductor layer. The superlattice layer may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include diffusing nitrogen into the superlattice layer.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 30, 2020
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, LOUIS NICHOLAS HUTTER, III
  • Patent number: 10593761
    Abstract: A method for making a semiconductor device may include forming spaced apart source and drain regions in a semiconductor layer with a channel region extending therebetween. At least one of the source and drain regions may be divided into a lower region and an upper region by a dopant diffusion blocking superlattice with the upper region having a same conductivity and higher dopant concentration than the lower region. The method may further include forming a gate on the channel region, depositing at least one metal layer on the upper region, and applying heat to move upward non-semiconductor atoms from the non-semiconductor monolayers to react with the at least one metal layer to form a contact insulating interface between the upper region and adjacent portions of the at least one metal layer.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 17, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Publication number: 20200075731
    Abstract: A method for making a semiconductor device may include forming a superlattice on a substrate comprising a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Moreover, forming at least one of the base semiconductor portions may include overgrowing the at least one base semiconductor portion and etching back the overgrown at least one base semiconductor portion.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20200075327
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: Keith Doran WEEKS, Nyles Wynn CODY, Marek HYTHA, Robert J. MEARS, Robert John STEPHENSON
  • Patent number: 10580866
    Abstract: A semiconductor device may include a semiconductor layer, spaced apart source and drain regions in the semiconductor layer with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The at least one dopant diffusion blocking superlattice comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10580867
    Abstract: A FINFET may include a semiconductor fin, spaced apart source and drain regions in the semiconductor fin with a channel region extending therebetween, and at least one dopant diffusion blocking superlattice dividing at least one of the source and drain regions into a lower region and an upper region with the upper region having a same conductivity and higher dopant concentration than the lower region. The dopant diffusion blocking superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a gate on the channel region.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: March 3, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Hideki Takeuchi, Daniel Connelly, Marek Hytha, Richard Burton, Robert J. Mears
  • Patent number: 10566191
    Abstract: A semiconductor device may include a substrate and a superlattice on the substrate including a plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Furthermore, an upper portion of at least one of the base semiconductor portions adjacent the respective at least one non-semiconductor monolayer may have a defect density less than or equal to 1×105/cm2.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 18, 2020
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10468245
    Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: November 5, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10453945
    Abstract: A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: October 22, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Hideki Takeuchi, Marek Hytha
  • Publication number: 20190279869
    Abstract: A method for making a semiconductor device may include forming a recess in a substrate including a first Group IV semiconductor, forming an active layer comprising a Group III-V semiconductor within the recess, and forming a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The method may further include forming an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: KEITH DORAN WEEKS, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Publication number: 20190279868
    Abstract: A semiconductor device may include a substrate including a first Group IV semiconductor having a recess therein, an active layer comprising a Group III-V semiconductor within the recess, and a buffer layer between the substrate and active layer and comprising a second Group IV semiconductor. The semiconductor device may further include an impurity and point defect blocking superlattice layer adjacent the buffer layer.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson
  • Patent number: 10361243
    Abstract: A method for making a CMOS image sensor may include forming a plurality of laterally adjacent infrared (IR) photodiode structures on a semiconductor substrate having a first conductivity type. Forming each IR photodiode structure may include forming a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may have the first conductivity type. A semiconductor layer may be formed on the superlattice, along with a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well above the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: July 23, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Marek Hytha
  • Publication number: 20190189677
    Abstract: A method for making a CMOS image sensor may include forming a plurality of laterally adjacent infrared (IR) photodiode structures on a semiconductor substrate having a first conductivity type. Forming each IR photodiode structure may include forming a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and a non-semiconductor monolayer(s) constrained within a crystal lattice of adjacent base semiconductor portions. The superlattice may have the first conductivity type. A semiconductor layer may be formed on the superlattice, along with a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well above the retrograde well having the first conductivity type.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: ROBERT J. MEARS, MAREK HYTHA
  • Patent number: 10276625
    Abstract: A CMOS image sensor may include a semiconductor substrate having a first conductivity type, and a plurality of laterally adjacent infrared (IR) photodiode structures on the substrate. Each IR photodiode structure may include a superlattice on the semiconductor substrate including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, the superlattice may have the first conductivity type. The CMOS image sensor may further include a semiconductor layer on the superlattice, a retrograde well extending downward into the semiconductor layer from a surface thereof and having a second conductivity type, a first well around a periphery of the retrograde well having the first conductivity type, and a second well within the retrograde well having the first conductivity type.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 30, 2019
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Marek Hytha