Abstract: According to one embodiment, a secure computing method includes setting a coefficient selected from a ring of integers Q based on first data X, generating n pieces of first fragment data from the first data X based on the coefficient, causing a learning model held in the computing device to learn the first fragment data, generating n pieces of second fragment data from second data Z based on the coefficient, performing, by each of the n computing devices, inference based on the second fragment data using the learning model, and obtaining decoded data dec by decoding k pieces of inference result data. The coefficient is set to make each of the n pieces of first fragment data less than a maximum value of the ring of integers Q.

Abstract: According to one embodiment, each of the client terminals includes a first processor configured to execute a learning process of machine learning model, extract a first parameter column from the machine learning model, change the arrangement of parameters, perform secret sharing with respect to the first parameter column, and transmit a first fragment parameter column. Each of the aggregated server device includes a second processor configured to receive first fragment parameter columns, change arrangement of fragment parameters, and execute an aggregation process. The machine learning model is updated based on parameters in a second parameter column decoded from second fragment parameter columns generated in the aggregated server devices.

Abstract: According to an embodiment, a quantum cryptographic communication system includes a first quantum key distribution (QKD) device, and a first key management device. The first QKD device that shares a quantum encryption key with a second QKD device through QKD. The first key management device includes a reception unit and a first hardware security module (HSM). The reception unit receives the quantum encryption key from the first QKD device. The first HSM includes a storage unit, a generation unit, and a first encryption unit. The storage unit stores a first encryption key therein. The generation unit generates an application key used in an encryption process by a cryptographic application. The first encryption unit that encrypts, with the first encryption key, the application key transmitted to a second key management device connected to the second QKD device.

Abstract: A quantum-cryptographic-communication system according to an embodiment includes a key-integrated-management device, quantum-cryptography devices, and key-management-inspection devices. An inspection-target-value-calculating unit calculates an inspection-target value based on quantum-cryptography-device information related to a quantum-cryptography device. An expected-value-calculating unit calculates an expected value based on at least one of wiring information of a QKD link connected to the inspection-target-quantum-cryptography device; weather information of the site installed with the inspection-target-quantum-cryptography device; and the quantum-cryptography-device information. A permissible-value-calculating unit calculates a permissible value based on at least one of the wiring information, the weather information, and the quantum-cryptography-device information.

Abstract: According to one embodiment, a secure computing method includes setting a coefficient selected from a ring of integers Q based on first data X, generating n pieces of first fragment data from the first data X based on the coefficient, causing a learning model held in the computing device to learn the first fragment data, generating n pieces of second fragment data from second data Z based on the coefficient, performing, by each of the n computing devices, inference based on the second fragment data using the learning model, and obtaining decoded data dec by decoding k pieces of inference result data. The coefficient is set to make each of the n pieces of first fragment data less than a maximum value of the ring of integers Q.

Abstract: A learning system according to an embodiment includes a model generation device and n calculation devices. The model generation device includes a splitting unit, a secret sharing unit, and a share transmission unit. The splitting unit splits m×n pieces of training data into n groups each including m training data pieces, the n groups corresponding to the respective n calculation devices on one-to-one basis. The secret sharing unit generates m distribution training data pieces for each of the n groups by distributing using a secret sharing scheme and generates distribution training data for each of the m training data pieces in an i-th group among the n groups, using an i-th element Pi among n elements P1, P2, . . . , Pi, . . . , Pn, by distributing using the secret sharing scheme. The share transmission unit transmits corresponding m distribution training data pieces to each of the n calculation devices.

Abstract: According to one embodiment, an anomaly detection device includes predicted value calculation unit, an anomaly degree calculation unit, a second predicted value calculation unit, a determination value calculation unit, and an anomaly determination unit. The first predicted value calculation unit calculates a first model predicted value from a correlation model obtained by first machine learning, the anomaly degree calculation unit calculates an anomaly degree, the second predicted value calculation unit calculates a second model predicted value from a time series model obtained by second machine learning, the determination value calculation unit calculates a divergence degree, and the anomaly determination unit determines whether an anomaly occurs or not.

Abstract: According to an embodiment, an arithmetic device is configured to receive M input signals each representing a two-state value and M coefficients to output an output signal representing a two-state value. The device includes a positive-side current source, a negative-side current source, M cross switches, a coefficient memory unit, and a comparator. The positive-side current source is configured to output a first voltage corresponding to a value of 1/L of the current output from a positive-side terminal. The negative-side current source is configured to output a second voltage corresponding to a value of 1/L of the current output from a negative-side terminal. The memory unit includes M cells corresponding to the respective M coefficients. The comparator is configured to output an output signal having a value corresponding to a comparison result of the first voltage with the second voltage. Each M cell includes a first resistor and a second resistor.

Abstract: An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.

Abstract: An integrated circuit according to an embodiment includes: first and second wiring lines; a memory device including a first and second terminals connected to the first and second wiring line respectively; a first transistor including a high-k metal gate; a first circuit applying a first write voltage between the first and the second terminals, and switch the resistance of the memory device from a high-resistance state to a low-resistance state; a second circuit reading the resistance of the memory device, and comparing a read value of the resistance with a predetermined value; a third circuit lowering a threshold voltage of the first transistor when the read value of the resistance is greater than the predetermined value; a fourth circuit applying a second write voltage between the first and second terminals after the threshold voltage is lowered; and a fifth circuit raising the threshold voltage of the first transistor.

Abstract: A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.

Abstract: An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a third terminal connected to the second terminal, and a fourth terminal; a first wiring line connected to the first terminal of the anti-fuse element; and a drive circuit configured to supply a plurality of potentials to the first terminal of the anti-fuse element, the drive circuit being connected to the first wiring line, the potentials being different from each other.

Abstract: A semiconductor integrated circuit according to an embodiment includes a plurality of first wiring lines electrically connected to a plurality of input wiring lines; a plurality of second wiring lines electrically connected to a plurality of output wiring lines, the second wiring lines crossing the first wiring lines; and a plurality of cell arrays each of which includes memory elements disposed at intersection regions of a part of the first wiring lines and a part of the second wiring lines, each of the memory elements including a first terminal and a second terminal, the first terminal being electrically connected to one of the first wiring lines, the second terminal being electrically connected to one of the second wiring lines, and each of the second wiring lines being electrically connected to at most one of the cell arrays.

Abstract: According to one embodiment, an integrated circuit includes first and second data lines, a first memory cell includes first and second resistance changing elements connected in series between the first and second data lines and a first selection transistor including a drain connected to a connection node of the first and second resistance changing elements, and a second memory cell includes third and fourth resistance changing elements connected in series between the first and second data lines and a second selection transistor including a drain connected to a connection node of the third and fourth resistance changing elements.

Abstract: An integrated circuit according to an embodiment includes: an anti-fuse element including a first terminal and a second terminal; a fuse element including a third terminal connected to the second terminal, and a fourth terminal; a first wiring line connected to the first terminal of the anti-fuse element; and a drive circuit configured to supply a plurality of potentials to the first terminal of the anti-fuse element, the drive circuit being connected to the first wiring line, the potentials being different from each other.

Abstract: A nonvolatile memory according to an embodiment includes a memory cell, the memory cell including: a memory transistor including a source, a drain, a gate electrode disposed above a channel between the source and the drain, and a gate insulating film disposed between the channel and the gate electrode; and a fuse element disposed between the gate electrode and a wiring line to which the gate electrode of the memory transistor is connected.

Abstract: A semiconductor integrated circuit according to an embodiment includes a plurality of first wiring lines electrically connected to a plurality of input wiring lines; a plurality of second wiring lines electrically connected to a plurality of output wiring lines, the second wiring lines crossing the first wiring lines; and a plurality of cell arrays each of which includes memory elements disposed at intersection regions of a part of the first wiring lines and a part of the second wiring lines, each of the memory elements including a first terminal and a second terminal, the first terminal being electrically connected to one of the first wiring lines, the second terminal being electrically connected to one of the second wiring lines, and each of the second wiring lines being electrically connected to at most one of the cell arrays.

Abstract: A programmable logic circuit includes: first to third wiring lines, the second wiring lines intersecting with the first wiring lines; and cells provided in intersecting areas, at least one of cells including a first transistor and a programmable device with a first and second terminals, the first terminal connecting to one of a source and a drain of the first transistor, the second terminal being connected to one of the second wiring lines, the other of the source and the drain being connected to one of the first wiring lines, and a gate of the first transistor being connected to one of the third wiring lines. One of source and drain of each of the first cut-off transistors is connected to the one of the second wiring lines, and an input terminal of each of first CMOS inverters is connected to the other of the source and the drain.

Abstract: A reconfigurable circuit according to an embodiment includes: first wiring lines; second wiring lines crossing the first wiring lines; resistive change elements disposed in intersection regions of the first and second wiring lines, each of the resistive change elements including a first terminal connected to the one of the first wiring lines and a second terminal connected to the one of the second wiring lines, and being switchable between a low-resistance state and a high-resistance state; a first control circuit controlling a voltage to be applied to the first wiring lines; a second control circuit controlling a voltage to be applied to the second wiring lines; and current limiting elements corresponding to the second wiring lines, and controlling current flowing through the resistive change elements connected to the corresponding second wiring line.

Abstract: A programmable logic circuit according to an embodiment includes: a first programmable device with a first and second terminals, a resistance of the first programmable device being changeable from a high resistance to a low resistance; a second programmable device with a third and fourth terminals, a resistance of the second programmable device being changeable from a high resistance to a low resistance; a first wiring line to which the first terminal is connected; a second wiring line to which the third terminal is connected; a third wiring line to which the second terminal and the fourth terminal are connected; and a fuse element of which one terminal is connected to the third wiring line.