Abstract: An implantable device includes a substrate and protective cover that cooperate to define an enclosed sensor volume. A sealed enclosure is provided within the sensor volume, with an electronic component assembly (ECA) being located within the sealed enclosure. A flexible circuit board assembly (FCBA) is electrically coupled with the ECA through a wall of the sealed enclosure. At least one transducer is provided on the FCBA in contact with the substrate, and the FCBA is held apart from the enclosure via a polymeric spacer provided therebetween. An inert polymer fill is provided within the sensor volume external to the enclosure.

Abstract: An implantable device includes a substrate and protective cover that cooperate to define an enclosed sensor volume. A sealed enclosure is provided within the sensor volume, with an electronic component assembly (ECA) being located within the sealed enclosure. A flexible circuit board assembly (FCBA) is electrically coupled with the ECA through a wall of the sealed enclosure. At least one transducer is provided on the FCBA in contact with the substrate, and the FCBA is held apart from the enclosure via a polymeric spacer provided therebetween. An inert polymer fill is provided within the sensor volume external to the enclosure.

Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.

Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

Abstract: An example embodiment may include a method for placing on a carrier substrate a semiconductor device. The method may include providing a semiconductor substrate comprising a rectangular shaped assist chip, which may include at least one semiconductor device surrounded by a metal-free border. The method may also include dicing the semiconductor substrate to singulate the rectangular shaped assist chip. The method may further include providing a carrier substrate having adhesive thereon. The method may additionally include transferring to and placing on the carrier substrate the rectangular shaped assist chip, thereby contacting the adhesive with the rectangular shaped assist chip at least at a location of the semiconductor device. The method may finally include singulating the semiconductor device, while remaining attached to the carrier substrate by the adhesive, by removing a part of rectangular shaped assist chip other than the semiconductor device.

Abstract: A surgical insertion device is disclosed, comprising an elongated central flat region tapering from one distal end having a device area, configured to receive an electronic device, towards the opposite distal end having a sharp tip.

Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

Abstract: A sensor for biopotential measurement, comprising: an electrical contacting unit for establishing an electrical contact with an animal or human skin, the electrical contacting unit being resilient. The sensor comprises a housing comprising a cavity wherein the electrical contacting unit is partially secured, and means for maintaining said electrical contacting unit in a resiliently deformed state when in contact with said skin.

Abstract: A method according to embodiments of the present invention comprises providing a magnetic stack comprising a magnetic layer sub-stack comprising magnetic layers and a bottom conductive electrode and a top conductive electrode electrically connecting the magnetic layer sub-stack at opposite sides thereof; providing a sacrificial pillar on top of the magnetic stack, the sacrificial pillar having an undercut with respect to an overlying second sacrificial material and a sloped foot with increasing cross-sectional dimension towards the magnetic stack, using the sacrificial pillar for patterning the magnetic stack, depositing an insulating layer around the sacrificial pillar, selectively removing the sacrificial pillar, thus creating a contact hole towards the patterned magnetic stack, and filling the contact hole with electrically conductive material.

Abstract: A method is disclosed for packaging a device, e.g., for bio-medical applications. In one aspect, the method includes obtaining a component on a substrate and separating the component and a first part of the substrate from a second part of the substrate using at least one physical process inducing at least one sloped side wall on the first part of the substrate. The method also includes providing an encapsulation for the chip. The resulting packaged chip advantageously has a good step coverage resulting in a good hermeticity, less sharp edges resulting in a reduced risk of damaging or infection after implantation and has a relatively small packaged volume compared to conventional big box packaging techniques.

Abstract: A method according to embodiments of the present invention comprises providing a magnetic stack comprising a magnetic layer sub-stack comprising magnetic layers and a bottom conductive electrode and a top conductive electrode electrically connecting the magnetic layer sub-stack at opposite sides thereof; providing a sacrificial pillar on top of the magnetic stack, the sacrificial pillar having an undercut with respect to an overlying second sacrificial material and a sloped foot with increasing cross-sectional dimension towards the magnetic stack, using the sacrificial pillar for patterning the magnetic stack, depositing an insulating layer around the sacrificial pillar, selectively removing the sacrificial pillar, thus creating a contact hole towards the patterned magnetic stack, and filling the contact hole with electrically conductive material.

Abstract: A method is described for setting up the lithographic processing of a substrate. The lithographic processing typically is characterized by a set of selectable process parameters, such as the thickness, real refractive index, and absorption coefficient of a bottom anti-reflective layer. The method includes selecting a set of values for the selectable process parameters, determining the substrate reflectivity in the resist layer for these parameters, and evaluating if the determined substrate reflectivity is smaller than a maximum allowable substrate reflectivity in the resist layer. The maximum allowable substrate reflectivity is determined according to a floating criterion, i.e., the maximum allowable substrate reflectivity depends on a Normalized Image Log Slope related parameter.

Abstract: Methods and systems are described for improving optical lithographic processing of a substrate by selecting appropriate system parameters in order to obtain a good image or print of the pattern to be obtained in a resist layer, which includes selecting a set of system parameters for an optical lithographic system having selectable system parameters, thus characterising the optical lithographic system and obtaining transferred lens pupil information. The latter is performed by obtaining, for each point of a set of points within a lens pupil of the optical lithographic system with the selected set of system parameters, a value of at least one optical parameter at a level of the substrate, the at least one optical parameter being a property of a light ray projected towards the substrate from the point of the set of points within the lens pupil. The lens pupil information then is combined with information about the mask to be used for generating the pattern in the resist layer.

Abstract: In the present invention, a BARC stack comprising at least a first BARC layer and at least a second BARC layer is optimized for reducing substrate reflectivity in lithographic processing applications. The first BARC layer is positioned adjacent the resist layer, while the second BARC layer is positioned adjacent the first BARC layer. The optical parameters of the first BARC layer are determined to be slightly different from the optical parameters of the resist, thus resulting in a small optical step at the interface resist/first BARC. Furthermore, the second BARC may be selected to have optical parameters such that the optical step at the interface first BARC/second BARC is slightly larger but still relatively small compared to the optical step between resist and substrate. The thicknesses for the BARC layers can be determined from substrate reflectivity calculations. The latter allows obtaining a low substrate reflectivity for various pitches in a pattern to be printed.

Abstract: A method is described for setting up the lithographic processing of a substrate. The lithographic processing typically is characterized by a set of selectable process parameters, such as the thickness, real refractive index, and absorption coefficient of a bottom anti-reflective layer. The method includes selecting a set of values for the selectable process parameters, determining the substrate reflectivity in the resist layer for these parameters, and evaluating if the determined substrate reflectivity is smaller than a maximum allowable substrate reflectivity in the resist layer. The maximum allowable substrate reflectivity is determined according to a floating criterion, i.e., the maximum allowable substrate reflectivity depends on a Normalized Image Log Slope related parameter.

Abstract: In the present invention, a BARC stack comprising at least a first BARC layer and at least a second BARC layer is optimized for reducing substrate reflectivity in lithographic processing applications. The first BARC layer is positioned adjacent the resist layer, while the second BARC layer is positioned adjacent the first BARC layer. The optical parameters of the first BARC layer are determined to be slightly different from the optical parameters of the resist, thus resulting in a small optical step at the interface resist/first BARC. Furthermore, the second BARC may be selected to have optical parameters such that the optical step at the interface first BARC/second BARC is slightly larger but still relatively small compared to the optical step between resist and substrate. The thicknesses for the BARC layers can be determined from substrate reflectivity calculations. The latter allows obtaining a low substrate reflectivity for various pitches in a pattern to be printed.

Abstract: A method is described for setting up lithographic processing of a substrate. The lithographic processing uses a bottom anti-reflective coating for minimizing the substrate reflectivity. Such bottom anti-reflective coating typically is characterized by a set of selectable BARC parameters, such as the thickness, real refractive index, and/or absorption coefficient. The method includes selecting a set of values for the BARC parameters, determining the substrate reflectivity in the resist layer using the selected BARC parameter values, thereby taking into account the angles of incidence of the incident light rays, and evaluating whether or not the selected BARC parameter values result in a sufficiently low substrate reflectivity. Preferably, together with taking into account the angles of incidence of the incident light rays, the amplitude and/or the polarization state for light rays having a different angle of incidence are also taken into account.

Abstract: Methods and systems are described for improving optical lithographic processing of a substrate by selecting appropriate system parameters in order to obtain a good image or print of the pattern to be obtained in a resist layer, which includes selecting a set of system parameters for an optical lithographic system having selectable system parameters, thus characterising the optical lithographic system and obtaining transferred lens pupil information. The latter is performed by obtaining, for each point of a set of points within a lens pupil of the optical lithographic system with the selected set of system parameters, a value of at least one optical parameter at a level of the substrate, the at least one optical parameter being a property of a light ray projected towards the substrate from the point of the set of points within the lens pupil. The lens pupil information then is combined with information about the mask to be used for generating the pattern in the resist layer.

Abstract: An organic silane compound for forming an antireflection film on the surface of a substrate prior to forming a resist pattern includes a silicon atom, a leaving group bound to the silicon atom and capable of reacting with a hydroxyl group existing in the surface of the semiconductor substrate to form a covalent bond between the semiconductor substrate and the organic silane compound, and a substituent group capable of absorbing far-ultra violet light. The substrate is coated with the organic silane compound. Resist is applied onto the substrate coated with the organic silane compound. The resist is exposed selectively using far-ultra violet light. The resist is exposed.