Patents by Inventor Maria V. Henao

Maria V. Henao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated core microelectronic package
    Patent number: 6825063
    Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 30, 2004
    Assignee: Intel Corporation
    Inventors: Quat T. Vu, Jian Li, Qing Ma, Maria V. Henao, Chun Mu
  • Integrated core microelectronic package
    Publication number: 20040094830
    Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.
    Type: Application
    Filed: June 30, 2003
    Publication date: May 20, 2004
    Applicant: Intel Corporation
    Inventors: Quat T. Vu, Jian Li, Qing Ma, Maria V. Henao, Xiao-Chun Mu
  • Integrated core microelectronic package
    Patent number: 6586822
    Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.
    Type: Grant
    Filed: September 8, 2000
    Date of Patent: July 1, 2003
    Assignee: Intel Corporation
    Inventors: Quat T. Vu, Jian Li, Qing Ma, Maria V. Henao, Xiao-Chun Mu
  • Microelectronic package having an integrated heat sink and build-up layers
    Publication number: 20020070443
    Abstract: A microelectronic package fabrication technology that attaches at least one microelectronic die onto a heat spreader and encapsulates the microelectronic die/dice thereon which may further include a microelectronic packaging core abutting the heat spreader wherein the microelectronic die/dice reside within at least one opening in a microelectronic package core. After encapsulation, build-up layers may be fabricated to form electrical connections with the microelectronic die/dice.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 13, 2002
    Inventors: Xiao-Chun Mu, Qing Ma, Maria V. Henao, Steven Towle, Quat T. Vu