Patents by Inventor Mariano Tepper

Mariano Tepper has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240427596
    Abstract: Systems, apparatuses and methods may provide for technology that conducts, in accordance with a first instruction, a load of a block of data into a register, wherein the block of data is to include a plurality of lanes, conducts, in accordance with a second instruction, a first bitwise mask application to each lane in the plurality of lanes, and extracts a set of vector dimensions from the block of data based on the first bitwise mask application.
    Type: Application
    Filed: August 12, 2024
    Publication date: December 26, 2024
    Inventors: Mark Hildebrand, Mariano Tepper, Maria Cecilia Aguerrebere Otegui, Ishwar Singh Bhati, Theodore Willke
  • Publication number: 20240419674
    Abstract: Technology as described herein provides for accessing input vectors and a query vector, the input vectors each having a dimensionality, the query vector associated with a query and having a dimensionality, applying a first vector transformation to the input vectors to generate primary vectors, each of the primary vectors having a dimensionality smaller than the dimensionality associated with the input vectors, applying a second vector transformation to the query vector to generate a modified query vector, the modified query vector having a dimensionality smaller than the dimensionality of the query vector, and conducting a similarity search on the primary vectors based on the modified query vector to generate one or more candidates for the query. In embodiments a first component of the first vector transformation is determined based on an algorithm and a second component of the second vector transformation is determined based on the same algorithm.
    Type: Application
    Filed: August 30, 2024
    Publication date: December 19, 2024
    Inventors: Mariano Tepper, Ishwar Singh Bhati, Maria Cecilia Aguerrebere Otegui, Mark Hildebrand, Theodore Willke
  • Publication number: 20240394310
    Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of means based on a plurality of vectors, wherein each mean in the plurality of means corresponds to center of a cluster, assigns each vector in a plurality of vectors to a mean in the plurality of means, and conducts a compression of the plurality of vectors based on the plurality of means. The technology may also build a directed graph based on the compressed plurality of vectors and update the directed graph. Updating the graph may involve determining a plurality of modified means, detecting that a change in one or more modified means in the plurality of modified means exceeds a threshold, conducting an update of the modified mean(s), and bypassing the update for one or more remaining means in the plurality of modified means.
    Type: Application
    Filed: August 8, 2024
    Publication date: November 28, 2024
    Inventors: Maria Cecilia Aguerrebere Otegui, Ishwar Singh Bhati, Mark Hildebrand, Mariano Tepper, Theodore Willke
  • Patent number: 11989553
    Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: May 21, 2024
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson
  • Publication number: 20240020308
    Abstract: Systems, apparatuses and methods may provide for technology that conducts a traversal of a directed graph in response to a query, retrieves the plurality of vectors from a dynamic random access memory (DRAM) in accordance with the traversal of the directed graphs, wherein each vector in the plurality of vectors is compressed, decompresses the plurality of vectors, determines a similarity between the query and the decompressed plurality of vectors, and generates a response to the query based on the similarity between the query and the decompressed plurality of vectors.
    Type: Application
    Filed: August 3, 2023
    Publication date: January 18, 2024
    Inventors: Maria Cecilia Aguerrebere Otegui, Ishwar Bhati, Mark Hildebrand, Mariano Tepper, Theodore Willke
  • Patent number: 11861494
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a cognitive space that is to be a compressed representation of activations of a neural network, maps a plurality of activations of the neural network to a cognitive initial point and a cognitive destination point in the cognitive space and generates a first cognitive trajectory through the cognitive space, wherein the first cognitive trajectory traverses the cognitive space from the cognitive initial point to the cognitive destination point.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Javier Felip Leon, Javier Sebastian Turek, David Israel Gonzalez Aguirre, Ignacio J. Alvarez, Javier Perez-Ramirez, Mariano Tepper
  • Patent number: 11853766
    Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.
    Type: Grant
    Filed: July 25, 2022
    Date of Patent: December 26, 2023
    Assignee: Intel Corporation
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Patent number: 11829376
    Abstract: Technologies for refining stochastic similarity search candidates include a device having a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Additionally, the circuitry is configured to identify a result set of the binary dimensionally expanded vectors as a function of a Hamming distance of each binary dimensionally expanded vector from the search hash code and determine, from the result set, a refined result set as a function of a similarity measure in an original input space of the input data vectors.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Jawad Khan, Sourabh Dongaonkar, Chetan Chauhan, Richard Coulson, Theodore Willke
  • Publication number: 20230305709
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.
    Type: Application
    Filed: September 15, 2020
    Publication date: September 28, 2023
    Inventors: Dipanjan Sengupta, Mariano Tepper, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson
  • Patent number: 11702105
    Abstract: Systems, apparatuses and methods may provide for technology that generates, via a first neural network such as a grid network, a first vector representing a prediction of future behavior of an autonomous vehicle based on a current vehicle position and a vehicle velocity. The technology may also generate, via a second neural network such as an obstacle network, a second vector representing a prediction of future behavior of an external obstacle based on a current obstacle position and an obstacle velocity, and determine, via a third neural network such as a place network, a future trajectory for the vehicle based on the first vector and the second vector, the future trajectory representing a sequence of planned future behaviors for the vehicle. The technology may also issue actuation commands to navigate the autonomous vehicle based on the future trajectory for the vehicle.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: July 18, 2023
    Assignee: Intel Corporation
    Inventors: Ignacio J. Alvarez, Vy Vo, Javier Felip Leon, Javier Perez-Ramirez, Javier Sebastian Turek, Mariano Tepper, David Israel Gonzalez Aguirre
  • Patent number: 11640295
    Abstract: Systems, apparatuses and methods may provide for technology that generates a dependence graph based on a plurality of intermediate representation (IR) code instructions associated with a compiled program code, generates a set of graph embedding vectors based on the plurality of IR code instructions, and determines, via a neural network, one of an analysis of the compiled program code or an enhancement of the program code based on the dependence graph and the set of graph embedding vectors. The technology may provide a graph attention neural network that includes a recurrent block and at least one task-specific neural network layer, the recurrent block including a graph attention layer and a transition function. The technology may also apply dynamic per-position recurrence-halting to determine a number of recurring steps for each position in the recurrent block based on adaptive computation time.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 2, 2023
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Bryn Keller, Mihai Capota, Vy Vo, Nesreen Ahmed, Theodore Willke
  • Patent number: 11620900
    Abstract: Systems, apparatuses and methods may provide for origination camera technology that generates a cell representation of a local space associated with an origination camera in a multicast domain, predicts that an object in the local space will exit the local space and enter one or more adjacent spaces associated with additional cameras in the multicast domain, and sends the cell representation and a trajectory of the object to the additional cameras before the object exits the local space. Additionally, transition camera technology may generate a leader election message based on a multicasted trajectory of an object and a predicted trajectory of the object, send the leader election message from a transition camera to one or more additional cameras in a multicast domain, and track the object in the local space in response to a leader notification message.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 4, 2023
    Assignee: Intel Corporation
    Inventors: Dario Oliver, Mateo Guzman, Mariano Tepper, Marcos Carranza, Javier Turek, Cesar Martinez-Spessot, Rita Wouhaybi, Javier Felip Leon
  • Patent number: 11604834
    Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Sourabh Dongaonkar, Chetan Chauhan, Jawad Khan, Theodore Willke, Richard Coulson, Rajesh Sundaram
  • Patent number: 11553129
    Abstract: Systems, apparatuses and methods may provide for technology that detects an unidentified individual at a first location along a trajectory in a scene based on a video feed of the scene, wherein the video feed is to be associated with a stationary camera, and selects a non-stationary camera from a plurality of non-stationary cameras based on the trajectory and one or more settings of the selected non-stationary camera. The technology may also automatically instruct the selected non-stationary camera to adjust at least one of the one or more settings, capture a face of the individual at a second location along the trajectory, and identify the unidentified individual based on the captured face of the unidentified individual.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Mateo Guzman, Javier Turek, Marcos Carranza, Cesar Martinez-Spessot, Dario Oliver, Javier Felip Leon, Mariano Tepper
  • Patent number: 11507773
    Abstract: Systems, apparatuses and methods may store a plurality of classes that represent a plurality of clusters in a cache. Each of the classes represents a group of the plurality of clusters and the plurality of clusters is in a first data format. The systems, apparatuses and methods further modify input data from a second data format to the first data format and conduct a similarity search based on the input data in the first data format to assign the input data to at least one class of the classes.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: November 22, 2022
    Assignee: Intel Corporation
    Inventors: Mariano Tepper, Dipanjan Sengupta, Theodore Willke, Javier Sebastian Turek
  • Patent number: 11500887
    Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 15, 2022
    Assignee: Intel Corporation
    Inventors: Sourabh Dongaonkar, Jawad B. Khan, Chetan Chauhan, Dipanjan Sengupta, Mariano Tepper, Theodore Willke, Richard L. Coulson
  • Publication number: 20220357951
    Abstract: An example system includes memory; a central processing unit (CPU) to execute first operations; in-memory execution circuitry in the memory; and detector software to cause offloading of second operations to the in-memory execution circuitry, the in-memory execution circuitry to execute the second operations in parallel with the CPU executing the first operations.
    Type: Application
    Filed: July 25, 2022
    Publication date: November 10, 2022
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Patent number: 11403102
    Abstract: Systems, apparatuses and methods may provide for technology that recognizes, via a neural network, a pattern of memory access and compute instructions based on an input set of machine instructions, determines, via a neural network, a sequence of instructions to be offloaded for execution by the secondary computing device based on the recognized pattern of memory access and compute instructions, and translates the sequence of instructions to be offloaded from instructions executable by a central processing unit (CPU) into instructions executable by the secondary computing device.
    Type: Grant
    Filed: June 27, 2020
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Vy Vo, Dipanjan Sengupta, Mariano Tepper, Javier Sebastian Turek
  • Patent number: 11392494
    Abstract: Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Jawad Khan, Chetan Chauhan, Rajesh Sundaram, Sourabh Dongaonkar, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper
  • Patent number: 11327881
    Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Chetan Chauhan, Sourabh Dongaonkar, Rajesh Sundaram, Jawad Khan, Sandeep Guliani, Dipanjan Sengupta, Mariano Tepper