Patents by Inventor Marie-Anne Jaud

Marie-Anne Jaud has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347545
    Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: July 9, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIOUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Sebastien Barnola, Marie-Anne Jaud, Jerome Mazurier, Nicolas Posseme
  • Publication number: 20180156749
    Abstract: Embodiments of the invention determine intrinsic parameters of stacked nanowires/nanosheets GAA MOSFETs comprising Nw nanowires and/or nanosheets, each nanowire/nanosheet being surrounded in an oxide layer, the oxide layers being embedded in a common gate, wherein the method comprises the following steps: measuring the following parameters of the MOSFET: number of stacked nanowires/nanosheets Nw, width Ww,i, of the nanowire/nanosheet number i, i being an integer from 1 to Nw, thickness of the nanowire/nanosheet Hw,i, number i, i being an integer from 1 to Nw, corner radius Rw,i of the nanowire/nanosheet number i, i being an integer from 1 to Nw, Rw,i; calculating, using a processor and the measured parameters, a surface potential x normalized by a thermal voltage ?T given by ?T=kBT/q; measuring the total gate capacitance for a plurality of gate voltages; determining, using the measured total gate capacitance and the calculated normalized surface potential, the intrinsic parameter of the stacked nanowire
    Type: Application
    Filed: November 30, 2017
    Publication date: June 7, 2018
    Inventors: Olivier ROZEAU, Marie-Anne JAUD, Joris LACORD, S├ębastien MARTINIE, Thierry POIROUX
  • Publication number: 20170358502
    Abstract: There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different characteristics, the method including producing at least one first gate pattern and at least one second gate pattern on the substrate; depositing, on the first and the second gate patterns, at least: a first protective layer, and a second protective layer overlying the first protective layer and made of a material different from that of the first protective layer; masking of the second gate pattern by a masking layer; isotropic etching of the second protective layer; removing the masking layer; and anisotropic etching of the second protective layer selectively relative to the first protective layer.
    Type: Application
    Filed: May 19, 2017
    Publication date: December 14, 2017
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Laurent GRENOUILLET, Sebastien BARNOLA, Marie-Anne JAUD, Jerome MAZURIER, Nicolas POSSEME
  • Publication number: 20160019327
    Abstract: A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 21, 2016
    Inventors: Thierry POIROUX, Marie-Anne JAUD, Sebastien MARTINIE, Olivier ROZEAU
  • Patent number: 9235668
    Abstract: A computer implemented method for calculating a charge density q1 of a first gate of a double gate transistor comprising a thin body with a first and a second gate interface, the method including determining, using a physical processor, an initial estimate q1,init of the charge density of the first gate; performing, using the physical processor, at least two basic corrections of the initial estimate based on a Taylor development of a function fzero(q1) able to be nullified by a correct value of the charge density q1 of the first gate.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: January 12, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Thierry Poiroux, Marie-Anne Jaud, Sebastien Martinie, Olivier Rozeau
  • Publication number: 20130203248
    Abstract: A method for producing an integrated circuit, including, in this order: a) producing at least one MOS electronic circuit and/or at least one level of electrical interconnections on a substrate; b) uniformly implantating dopants in at least a portion of a layer of crystalline semiconductor; c) thermally activating the dopants implanted in the portion of the crystalline semiconductor layer; d) rigidly connecting the crystalline semiconductor layer to the substrate; and e) producing at least one junctionless depletion-mode FET device including a part of the portion of the crystalline semiconductor layer.
    Type: Application
    Filed: June 6, 2011
    Publication date: August 8, 2013
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Thomas Ernst, Marie-Anne Jaud, Perrine Batude
  • Patent number: 8183630
    Abstract: A microelectronic device including: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor including a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by an insulating zone, and said insulating zone being constituted of several different dielectric materials include a first dielectric material and a second dielectric material.
    Type: Grant
    Filed: May 29, 2009
    Date of Patent: May 22, 2012
    Assignee: Commissariat A L'Energie Atomique
    Inventors: Perrine Batude, Laurent Clavelier, Marie-Anne Jaud, Olivier Thomas, Maud Vinet
  • Publication number: 20090294822
    Abstract: A microelectronic device comprising: a substrate surmounted by a stack of layers, at least one first transistor situated at a given level of said stack, at least one second transistor situated at a second level of said stack, above said given level, the first transistor comprising a gate electrode situated opposite a channel zone of the second transistor, the first transistor and the second transistor being separated by means of an insulating zone, said insulating zone having, in a first region between said gate of said first transistor and said channel of said second transistor, a composition and thickness provided so as to enable a coupling between the gate electrode of the first transistor and the channel of the second transistor, said insulating zone comprising a second region around the first region, between the access zones of the first and the second transistor of thickness and composition different to those of said first region.
    Type: Application
    Filed: May 29, 2009
    Publication date: December 3, 2009
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE
    Inventors: Perrine Batude, Laurent Clavelier, Marie-Anne Jaud, Olivier Thomas, Maud Vinet